# The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

- Moongyu Jang
^{1}Email author, - Youngsam Park
^{1}, - Myungsim Jun
^{1}, - Younghoon Hyun
^{1}, - Sung-Jin Choi
^{2}and - Taehyoung Zyung
^{1}

**5**:1654

**DOI: **10.1007/s11671-010-9690-2

© The Author(s) 2010

**Received: **21 June 2010

**Accepted: **1 July 2010

**Published: **18 July 2010

## Abstract

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K^{2} at room temperature.

### Keywords

Thermoelectric effect Seebeck coefficient Silicon Nanowire## Introduction

Thermoelectric device interconverts thermal gradient and electricity for power generation or cooling [1–3]. Traditionally, Bi_{2}Te_{3} semiconductor has been widely used as thermoelectric material due to its high thermoelectric performance, which has ZT = α^{2}
*σT*/*κ* ≈ 1, where *α, σ, κ* and T represent Seebeck coefficient, electrical conductivity, thermal conductivity and absolute temperature, respectively [4, 5]. However, thermoelectric devices based on Bi_{2}Te_{3} are difficult to miniaturize. In addition, according to the late tendency of development and production of products using Bi_{2}Te_{3} thermoelectric devices, supplies of Bi_{2}Te_{3} are predicted to face shortage soon. On the contrary, silicon is the most abundant semiconductor material with the matured fabrication infrastructure. One drawback in the consideration of silicon as thermoelectric material is the low ZT value (~0.01) due to its high *κ* value (~150 Wm^{−1}K^{−1}) at room temperature [6, 7]. Thus, silicon has been considered as the impropriate material for the thermoelectric applications. However, recent research revealed the possibility of silicon as thermoelectric material by incorporating nanotechnology. One-dimensional (nanostructured) silicon nanowire can dramatically reduce the phonon propagation through the nanowire while maintaining the electron/hole propagation property [8–10].

In this work, complementary metal-oxide-semiconductor (CMOS) compatible process is adopted to implement silicon thermoelectric device. By using conventional CMOS process, we have manufactured n-/p-type silicon nanowires, which correspond to n-/p-legs, respectively. The defined minimum width of silicon nanowire is 30 nm. The electrical conductivities are evaluated for the various nanowire widths. Also, Seebeck coefficient and maximum attainable power factor is evaluated from the manufactured n-/p-legs.

## Experimental Details

The <100>*p*-type 8-inch silicon-on-insulator (SOI) wafer is used to fabricate thermoelectric device. SOI wafer is boron doped with a resistivity of 13.5–22.5 Ω cm, and the corresponding doping concentration is about 1.0 × 10^{15} cm^{−3}. The thickness of the SOI and buried oxide (BOX) layer is 100 and 2,000 nm, respectively. SOI layer is thinned down to 40 nm using thermal oxidation method. BF_{2} and phosphorus atoms are doped for n-/p-leg formation using ion implantation method. And 160 nm wire patterns are defined by using KrF lithography technique. After photo-lithography step, O_{2} plasma ashing technique is adopted to reduce the wire width down to 30 nm. After the patterning of silicon nanowires using dry etching technique, 10 nm-thick titanium layer and 100-nm-thick platinum layer are sputtered and patterned using lift-off method. Titanium is used as adhesion layer between silicon and platinum. Platinum layer is used as heating source and temperature sensor.

## Results and Discussion

_{2}plasma ashing. As explained in the experimental details, 160-nm silicon patterns are defined photo-lithographically defined by using KrF scanner as shown in Fig. 1a. And by using O

_{2}plasma ashing technique, 160-nm patterns are reduced down to 30 nm as shown Fig. 1b. By using this technique, bunches of silicon nanowires can be patterned on the whole region of 8-inch wafer.

^{15}cm

^{−2}. The extracted electrical conductivity of 30-nm n-leg (σ

_{ n }) is 842 Ω

^{−1}cm

^{−1}, and the corresponding doping concentration is around 6.0 × 10

^{19}cm

^{−3}. P-leg is doped using BF

_{2}with the dose of 5 × 10

^{15}cm

^{−2}. The extracted electrical conductivity of 30 nm p-leg (σ

_{ p }) is 396 Ω

^{−1}cm

^{−1}, and the corresponding doping concentration is around 4.0 × 10

^{19}cm

^{−3}[11]. The decrease in electrical conductivities with the decrease in width is due to the finite line width effect.

*T*

_{C}) is set as 20°C, and the hot region temperature (

*T*

_{H}) is controlled from 20 to 42°C. The output voltage characteristics are measured in various nanowire widths of 30, 40, 100 and 150 nm. The output voltage linearly increases as the temperature increases in both n-/p-leg. The slope represents Seebeck coefficient. P-leg shows more sensitive response to the temperature than n-leg, which is typical characteristic in thermoelectric material [13].

_{ n }) varies from −77 to −94 μV/K depending on the width. In p-leg, Seebeck coefficient (α

_{ p }) varies from 108 to 122 μV/K. In the case of serial connection between n-leg and p-leg, the attainable Seebeck coefficient value (α) can be estimated using weighted average relation, i.e., α = (α

_{ n }σ

_{ n }+ α

_{ p }σ

_{ p })/(σ

_{ n }+ α

_{ p }) [2]. By applying this relation, the maximum attainable Seebeck coefficient is 105 μV/K in the case of serial connection between 30-nm n-leg and 40-nm p-leg. In this case, the maximum attainable power factor (α

^{2}·σ) is 0.74 mW K

^{−2}cm

^{−1}. By optimizing the doping concentration, nanowire width and process conditions, Seebeck coefficient should be increased up to 200 μV/K for the comparable property with Bi

_{2}Te

_{3}in power factor.

## Conclusions

CMOS compatible process is adopted to implement the real silicon thermoelectric device. By using conventional CMOS process, we have manufactured n-/p-type silicon nanowires. The defined minimum width of silicon nanowire is 30 nm. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg, respectively. The maximum attainable power factor is 0.74 mW/m K^{2} at room temperature.

## Declarations

### Open Access

This article is distributed under the terms of the Creative Commons Attribution Noncommercial License which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.

## Authors’ Affiliations

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