Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application
© Sahu et al; licensee Springer. 2011
Received: 20 September 2010
Accepted: 28 February 2011
Published: 28 February 2011
Ge nanocrystals (Ge-NCs) embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV) ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV) have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS) memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV) sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.
During the last decade, non-volatile memory (NVM) structures consisting of semiconductor nanocrystals (NCs), in particular, Si and Ge-NCs, embedded in a dielectric matrix have drawn considerable attraction because of their high endurance, low operating voltage, reduced lateral discharge path, low power consumption, larger retention, and faster operation [1–5]. Compared to Si-NC, utilization of Ge-NC as the floating gate material can give rise to enhanced device performance because of its smaller band gap, which provides both a higher confinement barrier for retention mode and a lower barrier for program/erase mode [4, 5]. Quantum confinement effects should also be higher in Ge than in Si because of its smaller electron and hole effective masses, higher dielectric constant, and larger excitonic Bohr radius [6, 7]. In recent studies, high-k gate dielectrics replaced the conventional SiO2 dielectric to be used as tunnel and control oxides in NVMs, which allows for a thinner equivalent oxide thickness without sacrificing the non-volatility [8–12]. Furthermore, the thicker physical thickness of the high-k dielectrics ensures good retention characteristics, while due to unique band asymmetry with Si, their lower electron barrier height allows for a larger tunneling current at low control gate voltage when the device operates in the programming regime [10, 12]. However, the trade-off between program/erase efficiency and data retention remains an important issue. One of the promising ways to improve the trade-off is to use an asymmetric tunnel barrier, which typically consists of double-stack insulating layers having different band-gap energies [13–15]. In previous studies, Wang and Lu  have implemented stacked HfO2/SiO2 tunnel layers and successfully fabricated uniform Ge-NCS with improved charge storage effect using electron-beam evaporation method. However, they have employed relatively thicker dielectric films for the evolution of Ge-NCs. In the present investigation, low-energy ion implantation method, which is fully compatible with the mainstream CMOS technology, has been employed for the formation of Ge-NCs in SiN matrix with thinner HfO2/SiO2 stack tunnel layers. In addition, taking advantage of the excellent diffusion barrier properties of Si3N4 , well-defined Ge-NCs are expected to be formed in the top nitride layer without any significant diffusion of Ge toward Si/tunnel oxide interface and/or to the surface of control layer by suitably varying the implantation parameters and annealing condition. The dependence of implantation energy for the formation and evolution of Ge-NCs in these stack structures were studied further.
Before ion implantation, 1.2 nm of SiO2 was thermally grown on p-type Si (100) substrates (resistivity 1-10 Ω cm). Subsequently, 4.7 nm of HfO2 were deposited by metal organic chemical vapor deposition technique. The top SiN layer with a thickness of about 12 nm was then deposited with electron cyclotron resonance plasma-enhanced chemical vapor deposition method under a flow of SiH4 and N2 (instead of NH3) to minimize the H content in the films. Ion implantation in these stack layers were carried out with 74Ge+ ions using GeH4 gas source for the extraction of Ge. The Ge+ ion implantation was carried out at two different energies of 3 and 5 keV, while the dose was kept constant at 1.5 × 1016 cm-2. These two sets of samples implanted at 3 and 5 keV are denoted as A3 and A5, respectively. The post-implanted samples were subjected to conventional furnace annealing at 800°C in highly pure dry N2 for 30 min for the evolution of Ge-NCs. For reference, some SiN/HfO2/SiO2 stack layers were treated under the same annealing condition without any Ge+ implantation and were defined as the control sample. The formation and evolution of Ge-NCs have been investigated using high-resolution electron microscopy (HREM) on cross-sectional specimens. Cross sectional samples were prepared by mechanical polishing and ion milling using the standard procedure. HREM images were taken using a field emission TEM (FEI Tecnai™ F20 operating at 200 kV) equipped with a spherical aberration corrector. Metal-insulator-semiconductor (MIS) memory capacitor structures were fabricated from the samples by evaporating Al electrodes with 0.8-mm diameter with a shadow mask and Al rear-side contact after scratching the back surface. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were carried out using HP4192A impdance analyzer through a LABVIEW interface.
Results and discussion
where ΔV fb is the measured flat-band shift, C ox is the total oxide capacitance, q is the electronic charge, and A is the top contact area. The trap charge density was estimated to be 5.7 × 1012 cm-2 (sample A5) and 0.78 × 1012 cm-2 (sample A3) at a sweeping voltage of ± 7 V, indicating that the significant charge storage in sample A5 is predominantly due to Ge-NCs. It is interesting to note that the C-V curve of sample A3 shows a significant positive shift compared to the control sample, indicating the existence of fixed negative charges in the dielectrics. It is speculated that sample A3 contains a significant amount of GeO x -type network. These dangling bond structures can then capture electrons and become negatively charged, thereby causing a positive shift of the C-V curves of sample A3. Similar observations have been reported for Ge-NCs embedded in a SiO2 matrix .
In summary, we have conducted a comparative investigation of Ge+ ion implantation energy-dependent memory effects in SiN dielectric layers with HfO2/SiO2 asymmetric tunnel barriers at a constant implantation dose of 1.5 × 1016 cm-2, and subsequent thermal annealing at 800°C in N2. For the lower Ge+ implantation energy of 3 keV, no Ge-NC was observed in the stack structures, and the resultant MIS structure exhibited a small memory window of 0.74 V, which is attributed to a net negative charge storage in GeO x -dangling bonds. In contrast, for the higher Ge+ implantation energy of 5 keV, nearly spherical and well-isolated Ge-NCs with an average size of 3.5 nm were self-assembled within the top Si3N4 layer at a distance of 5.6 nm from SiN/HfO2 interface. A significant memory window of 3.95 V has been achieved over a small voltage sweep range (≤6 V). Frequency-dependent C-V and G-V curves indicate negligible contribution from interfacial defects toward the charge storage capability. An extrapolated memory window of about 1.06 V is achievable for a waiting time of 10 years due to the charge confinement in Ge-NCs, indicating the utility of these Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si stack structures for low operating voltage NVM devices.
full width at half maximum
high-resolution electron microscopy
- Tiwari S, Rana F, Hartstein H, Crabbe EF, Chan K: A silicon nanocrystals based memory. Appl Phys Lett 1996, 68: 1377. 10.1063/1.116085View ArticleGoogle Scholar
- Hanafi HI, Tiwari S, Khan I: Fast and long retention-time nano-crystal memory. IEEE Trans Electron Dev 1996, 43: 1553. 10.1109/16.535349View ArticleGoogle Scholar
- Ng CY, Chen TP, Ding L, Fung S: Memory characteristics of MOSFETs with densely stacked silicon nanocrystal layers in the gate oxide synthesized by low-energy ion beam. IEEE Electron Dev Lett 2006, 27: 231. 10.1109/LED.2006.871183View ArticleGoogle Scholar
- King YC, King TJ, Hu C: Charge-trap memory device fabricated by oxidation of Si1-xGex. IEEE Trans Electron Dev 2001, 48: 696. 10.1109/16.915694View ArticleGoogle Scholar
- Kanoun M, Busseret C, Poncet A, Souifi A, Baron T, Gautier E: Electronic properties of Ge nanocrystals for nonvolatile memory applications. Solid-State Electron 2006, 50: 1310. 10.1016/j.sse.2006.07.006View ArticleGoogle Scholar
- Maeda Y: Visible photoluminescence from nanocrystallite Ge embedded in a glassy SiO2 matrix; Evidence in support of the quqntum-confinement mechanism. Phys Rev B 1995, 51: 1658. 10.1103/PhysRevB.51.1658View ArticleGoogle Scholar
- Okamoto S, Kanemitsu Y: Photoluminescence properties of surface-oxidized Ge nanocrystals; Surface localization of excitons. Phys Rev B 1996, 54: 16421. 10.1103/PhysRevB.54.16421View ArticleGoogle Scholar
- Wan Q, Zhang NL, Liu WL, Lin CL, Wang TH: Memory and negative photoconductivity effects of Ge nanocrystals embedded in ZrO2/Al2O 3 gate dielectrics. Appl Phys Lett 2003, 83: 138. 10.1063/1.1589196View ArticleGoogle Scholar
- Lu XB, Lee PF, Dai JY: Synthesis and memory effect study of Ge nanocrystals embedded in LaAlO3 high-k dielectrics. Appl Phys Lett 2005, 86: 203111. 10.1063/1.1926414View ArticleGoogle Scholar
- Kim DW, Kim T, Banerjee SK: Memory characterization of SiGe quantum dot flash memories with HfO2 and SiO2tunneling dielectrics. IEEE Trans Electron Dev 2003, 50: 1823. 10.1109/TED.2003.815370View ArticleGoogle Scholar
- Chan MY, Lee PS, Ho V, Seng HL: Ge nanocrystals in lanthanide-based Lu2O3 high-k dielectric for nonvolatile memory application. J Appl Phys 2007, 102: 094307. 10.1063/1.2803883View ArticleGoogle Scholar
- Lee JJ, Wang X, Bai W, Lu N, Kwong DL: Theoritical and experimental investigation of Si nanocrystal memory device with HfO2 high-k tunneling dielectric. IEEE Trans Electron Dev 2003, 50: 2067. 10.1109/TED.2003.816107View ArticleGoogle Scholar
- Matsumoto Y, Hanajiri T, Toyabe T, Sugano T: Single electron device with asymmetric tunnel barriers. Jpn J Appl Phys part 1 1996, 35: 1126. 10.1143/JJAP.35.1126View ArticleGoogle Scholar
- Likharev KK: Layered tunnel barriers for nonvolatile memory devices. Appl Phys Lett 1998, 73: 2137. 10.1063/1.122402View ArticleGoogle Scholar
- Blomme P, Van Houdt J, De Meyer K: Write/erase cycling endurance of memory cells with SiO2/HfO2 tunnel dielectric. IEEE Trans Dev Mater Reliab 2004, 4: 345. 10.1109/TDMR.2004.837120View ArticleGoogle Scholar
- Wang S, Lu W: Investigation of Ge nanocrystals in a metal-insulator-semiconductor structure with a HfO2/SiO2 stack as the tunnel dielectric. Appl Phys Lett 2005, 86: 113105. 10.1063/1.1864254View ArticleGoogle Scholar
- Tyschenko YE, Volodin VA, Rebohle L, Voelskov M, Skorupa V: Photoluminescence of Si3N4 films implanted with Ge+ and Ar+ ions. Semiconductors 1999, 33: 523. 10.1134/1.1187721View ArticleGoogle Scholar
- Claverie A, Bonafos C, Assayag GB, Schamm S, Cherkashin N, Pillard V, Dimitrakis P, Kapetenakis E, Tsoukalas D, Muller T, Schmidt B, Heinig KH, Perego M, Fanciulli M, Mathiot D, Carrada M, Normad P: Materials science issues for the fabrication of nanocrystal memory devices by ultra low energy ion implantation. Defect Diffus Forum 2006, 258–260: 531. 10.4028/www.scientific.net/DDF.258-260.531Google Scholar
- Carrada M, Bonafos C, Ben Assayag G, Chassaing D, Normad P, Tsoukalas D, Soncini V, Claverie A: Effect of ion energy and dose on the positioning of 2D-arrays of Si nanocrystals ion beam synthesized in thin SiO2 layers. Physica E 2003, 17: 513. 10.1016/S1386-9477(02)00855-XView ArticleGoogle Scholar
- Normad P, Kapetanakis E, Dimitrakis P, Skarlatos D, Beltsios K, Tsoukalas D, Bonafos C, Assayag GB, Cherkashin N, Claverie A, Van Den Berg JA, Soncini V, Agarwal A, Ameen M, Perego M, Fanciulli M: Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications. Nucl Instrum Methods B 2004, 216: 228. 10.1016/j.nimb.2003.11.039View ArticleGoogle Scholar
- Sargentis Ch, Giannakopoulos K, Travlos A, Boukos N, Tsamakis D: Simple method for the fabrication of a high dielectric constant metal-oxide-semiconductor capacitor embedded with pt nanoparticles. Appl Phys Lett 2006, 88: 073106. 10.1063/1.2174099View ArticleGoogle Scholar
- Shi Y, Saito K, Ishikuro H, Hiramoto T: Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals. J Appl Phys 1998, 84: 2358. 10.1063/1.368346View ArticleGoogle Scholar
- Choi WK, Chim WK, Heng CL, Teo LW, Ho V, Ng V, Antoniadis DA, Fitzgerald EA: Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-oxide-semiconductor structure. Appl Phys Lett 2002, 80: 2014. 10.1063/1.1459760View ArticleGoogle Scholar
- Park CJ, Cho KH, Wang WC, Cho HY, Choi SH, Elliman RG, Han JH, Kim C: Large capacitance-voltage hysteresis loops in SiO2 films containing Ge nanocrystals produced by ion implantation and annealing. Appl Phys Lett 2006, 88: 071916. 10.1063/1.2175495View ArticleGoogle Scholar
- Nicolian EH, Brews JR: MOS Physics and Technology. New York: Wiley; 1982.Google Scholar
- Simons AJ, Tayarani-Najaran MH, Thomas CB: Conductance technique measurementsof the density of interface states between ZnS;Mn and p-silicon. J Appl Phys 1991, 70: 4950. 10.1063/1.349042View ArticleGoogle Scholar
- Harris H, Biswas N, Temkin H, Gangopadhyay S, Strathman M: Plasma enhanced metalorganic chemical vapor deposition of amorphous aluminum nitride. J Appl Phys 2001, 90: 5825. 10.1063/1.1413484View ArticleGoogle Scholar
- Beenakker CW: Theory of Coulomb-blockade oscillations in the conductance of a quantum dot. Phys Rev B 1991, 44: 1646. 10.1103/PhysRevB.44.1646View ArticleGoogle Scholar
- Chiang KH, Lu SW, Peng YH, Kuang CH, Tsai CS: Characterization and modeling of fast traps in thermal agglomerating germanium nanocrystal metal-oxide-semiconductor capacitor. J Appl Phys 2008, 104: 014506. 10.1063/1.2953194View ArticleGoogle Scholar
- de Sousa JS, Freire VN, Leburton JP: Hole-versus electron-based operations in SiGe nanocrystal nonvolatile memories. Appl Phys Lett 2007, 90: 223504. 10.1063/1.2741598View ArticleGoogle Scholar
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