Scaling properties of ballistic nanotransistors
 Ulrich Wulf^{1}Email author,
 Marcus Krahlisch^{1} and
 Hans Richter^{1}
DOI: 10.1186/1556276X6365
© Wulf et al; licensee Springer. 2011
Received: 5 November 2010
Accepted: 28 April 2011
Published: 28 April 2011
Abstract
Recently, we have suggested a scaleinvariant model for a nanotransistor. In agreement with experiments a closetolinear threshold trace was found in the calculated I _{D}  V _{D}traces separating the regimes of classically allowed transport and tunneling transport. In this conference contribution, the relevant physical quantities in our model and its range of applicability are discussed in more detail. Extending the temperature range of our studies it is shown that a closetolinear threshold trace results at room temperatures as well. In qualitative agreement with the experiments the I _{D}  V _{G}traces for small drain voltages show thermally activated transport below the threshold gate voltage. In contrast, at large drain voltages the gatevoltage dependence is weaker. As can be expected in our relatively simple model, the theoretical drain current is larger than the experimental one by a little less than a decade.
Introduction
In the past years, channel lengths of fieldeffect transistors in integrated circuits were reduced to arrive at currently about 40 nm [1]. Smaller conventional transistors have been built [2–9] with gate lengths down to 10 nm and below. As wellknown with decreasing channel length the desired longchannel behavior of a transistor is degraded by shortchannel effects [10–12]. One major source of these shortchannel effects is the multidimensional nature of the electrostatic field which causes a reduction of the gate voltage control over the electron channel. A second source is the advent of quantum transport. The most obvious quantum shortchannel effect is the formation of a sourcedrain tunneling regime below threshold gate voltage. Here, the I _{D}  V _{D}traces show a positive bending as opposed to the negative bending resulting for classically allowed transport [13, 14]. The sourcedrain tunneling and the classically allowed transport regime are separated by a closeto linear threshold trace (LTT). Such a behavior is found in numerous MOSFETs with channel lengths in the range of a few tens of nanometers (see, for example, [2–9]).
Starting from a threedimensional formulation of the transport problem it is possible to construct a onedimensional effective model [14] which allows to derive scaleinvariant expressions for the drain current [15, 16]. Here, the quantity arises as a natural scaling length for quantum transport where ε _{F} is the Fermi energy in the source contact and m* is the effective mass of the charge carriers. The quantum shortchannel effects were studied as a function of the dimensionless characteristic length l = L/λ of the transistor channel, where L is its physical length.
In this conference contribution, we discuss the physics of the major quantities in our scaleinvariant model which are the chemical potential, the supply function, and the scaleinvariant current transmission. We specify its range of applicability: generally, for a channel length up to a few tens of nanometers a LTT is definable up to room temperature. For higher temperatures, a LTT can only be found below a channel length of 10 nm. An inspection of the I _{D}  V _{G}traces yields in qualitative agreement with experiments that at low drain voltages transport becomes thermally activated below the threshold gate voltage while it does not for large drain voltages. Though our model reproduces interesting qualitative features of the experiments it fails to provide a quantitative description: the theoretical values are larger than the experimental ones by a little less than a decade. Such a finding is expected for our simple model.
Theory
TsuEsaki formula for the drain current
where E _{ k = 1}is the bottom of the lowest twodimensional subband resulting in the zconfinement potential of the electron channel at zero drain voltage (see Figure 4b of Ref. [13]). The parameter W is the width of the transistor. Finally, V _{D} = eU _{D} is the drain potential at drain voltage U _{D} which is assumed to fall off linearly.
Here, F _{1/2} is the FermiDirac integral of order 1/2 and is the inverse function of F _{1/2}. The effective current transmission depends on which is the normalized energy of the electron motion in the yzplane while is their energy in the xdirection. In the next sections, we will discuss the occurring quantities in detail.
Chemical potential in source and draincontact
Supply function
Current transmission
with and .
To a large extent the Fowler Nordheim oscillations in the numerical transmission average out performing the integration in Equation 4.
Parameters in experimental nanoFETs
Heavily doped contacts
For n ^{++}doped Si contacts the valleydegeneracy is N _{V} = 6 and the effective mass is taken as . Here m _{1} = 0.19m _{0} and m _{2} = 0.98m _{0} are the effective masses corresponding to the principle axes of the constant energy ellipsoids. In our later numerical calculations we set ε _{F} = 0.35 eV assuming a level of sourcedoping as high as N _{i} = n _{0} = 10^{21} cm^{3}.
Electron channel
Here ε _{F} = 0.35 eV was assumed. One then has in Equation 3 I _{0} = ~ 27μ A and with λ ~ 1 nm as well as = 2 one obtains J _{0} = 5.4 × 10^{4} μ A/μ m.
Results
Drain characteristics
Threshold characteristics
Discussion
The experimental and the theoretical drain characteristics in Figure 7 look structurally very similar. For a quantitative comparison we recall from Sect. "Parameters in experimental nanoFETs" the value of J _{0} = 5.4 × 10^{4} μ A/μ m. Then the maximum value j = 0.15 in Figure 7b corresponds to a theoretical current per width of 8 × 10^{3} μ A/μ m. To compare with the experimental current per width we assume that in the yaxis labels in Figures 7a and 8a it should read μ A/μ m instead of A/μ m. The former unit is the usual one in the literature on comparable nanotransistors (see Refs. [2–9]) and with this correction the order of magnitude of the drain current per width agrees with that of the comparable transistors. It is found that the theoretical results are larger than the experimental ones by about a factor of ten. Such a failure has to be expected given the simplicity of our model. First, for an improvement it is necessary to proceed from potentials resulting in a selfconsistent calculation. Second, our representation of the transistor by an effectively onedimensional system probably underestimates the backscattering caused by the relatively abrupt transition between contacts and electron channel. Third, the drain current in a real transistor is reduced by impurity interaction, in particular, by inelastic scattering. As a final remark we note that in transistors with a gate length in the micrometer scale shortchannel effects may occur which are structurally similar to the ones discussed in this article (see Sect. 8.4 of [10]). Therefore, a quantitatively more reliable quantum calculation would be desirable allowing to distinguish between the shortchannel effects on micrometer scale and quantum shortchannel effects.
Summary
After a detailed discussion of the physical quantities in our scaleinvariant model we show that a LTT is present not only in the low temperature limit but also at room temperatures. In qualitative agreement with the experiments the I _{D}  V _{G}traces exhibit below the threshold voltage thermally activated transport at small drain voltages. At large drain voltages the gatevoltage dependence of the traces is much weaker. It is found that the theoretical drain current is larger than the experimental one by a little less than a decade. Such a finding is expected for our simple model.
Abbreviation
 LTT:

linear threshold trace.
Declarations
Authors’ Affiliations
References
 Auth C, Buehler H, Cappellani A, Choi Hh, Ding G, Han W, Joshi S, McIntyre B, Prince M, Ranade P, Sandford J, Thomas C: 45 nm Highk+Metal Gate StrainEnhanced Transistors. Intel Technol J 2008, 12: 77–85.
 Yu B, Wang H, Joshi A, Xiang Q, Ibok E, Lin MR: 15 nm Gate Length Planar CMOS Transistor. IEDM Tech Dig 2001, 937.
 Doris B, Ieong M, Kanarsky T, Zhang Y, Roy RA, Dokumaci O, Ren Z, Jamin FF, Shi L, Natzle W, Huang HJ, Mezzapelle J, Mocuta A, Womack S, Gribelyuk M, Jones EC, Miller RJ, Wong HSP, Haensch W: Extreme Scaling with UltraThin Si Channel MOSFETs. IEDM Tech Dig 2002, 267.
 Doyle B, Arghavani R, Barlage D, Datta S, Doczy M, Kavalieros J, Murthy A, Chau R: Transistor Elements for 30 nm Physical Gate Lengths. Intel Technol J 2002, 6: 42.
 Chau R, Doyle B, Doczy M, Datta S, Hareland S, Jin B, Kavalieros J, Metz M: Silicon NanoTransistors and Breaking the 10 nm Physical Gate Length Barrier. 61st Device Research Conference 2003; Salt Lake City, Utah (invited talk)
 Tyagi S, Auth C, Bai P, Curello G, Deshpande H, Gannavaram S, Golonzka O, Heussner R, James R, Kenyon C, Lee SH, Lindert N, Miu M, Nagisetty R, Natarajan S, Parker C, Sebastian J, Sell B, Sivakumar S, St Amur A, Tone K: An advanced low power, high performance, strained channel 65 nm technology. IEDM Tech Dig 2005, 1070.
 Natarajan S, Armstrong M, Bost M, Brain R, Brazier M, Chang CH, Chikarmane V, Childs M, Deshpande H, Dev K, Ding G, Ghani T, Golonzka O, Han W, He J, Heussner R, James R, Jin I, Kenyon C, Klopcic S, Lee SH, Liu M, Lodha S, McFadden B, Murthy A, Neiberg L, Neirynck J, Packan P, Pae S, Parker C, Pelto C, Pipes L, Sebastian J, Seiple J, Sell B, Sivakumar S, Song B, Tone K, Troeger T, Weber C, Yang M, Yeoh A, Zhang K: A 32 nm Logic Technology Featuring 2ndGeneration Highk + MetalGate Transistors, Enhanced Channel Strain and 0.171 μm ^{ 2 } SRAM Cell Size in a 291 Mb Array. IEDM Tech Dig 2008, 1.
 Fukutome H, Hosaka K, Kawamura K, Ohta H, Uchino Y, Akiyama S, Aoyama T: Sub30nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process. IEEE Electron Dev Lett 2008, 29: 765.View Article
 Bedell SW, Majumdar A, Ott JA, Arnold J, Fogel K, Koester SJ, Sadana DK: Mobility Scaling in ShortChannel Length Strained GeonInsulator PMOSFETs. IEEE Electron Dev Lett 2008, 29: 811.View Article
 Sze SM: Physics of Semiconductor Devices. New York: Wiley; 1981.
 Thompson S, Packan P, Bohr M: MOS Scaling: Transistor Challenges for the 21st Century. Intel Technol J 1998, Q3: 1.
 Brennan KF: Introduction to Semiconductor Devices. Cambridge: Cambridge University Press; 2005.View Article
 Nemnes GA, Wulf U, Racec PN: Nanotransistors in the LandauerBüttiker formalism. J Appl Phys 2004, 96: 596. 10.1063/1.1748858View Article
 Nemnes GA, Wulf U, Racec PN: Nonlinear IV characteristics of nanotransistors in the LandauerBüttiker formalism. J Appl Phys 2005, 98: 84308. 10.1063/1.2113413View Article
 Wulf U, Richter H: Scaling in quantum transport in silicon nanotransistors. Solid State Phenomena 2010, 156–158: 517.View Article
 Wulf U, Richter H: Scaleinvariant drain current in nanoFETs. J Nano Res 2010, 10: 49.View Article
 Ando T, Fowler AB, Stern F: Electronic properties of twodimensional systems. Rev Mod Phys 1982, 54: 437. 10.1103/RevModPhys.54.437View Article
 Stern F: SelfConsistent Results for nType Si Inversion Layers. Phys Rev B 1972, 5: 4891. 10.1103/PhysRevB.5.4891View Article
Copyright
This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.