A compact model for magnetic tunnel junction (MTJ) switched by thermally assisted Spin transfer torque (TAS + STT)
© Zhao et al; licensee Springer. 2011
Received: 2 November 2010
Accepted: 28 April 2011
Published: 28 April 2011
Thermally assisted spin transfer torque [TAS + STT] is a new switching approach for magnetic tunnel junction [MTJ] nanopillars that represents the best trade-off between data reliability, power efficiency and density. In this paper, we present a compact model for MTJ switched by this approach, which integrates a number of physical models such as temperature evaluation and STT dynamic switching models. Many experimental parameters are included directly to improve the simulation accuracy. It is programmed in the Verilog-A language and compatible with the standard IC CAD tools, providing an easy parameter configuration interface and allowing high-speed co-simulation of hybrid MTJ/CMOS circuits.
Today, most of the R&D efforts in MTJ are focused on its switching approaches, which are expected to be scalable, energy efficient, reliable and fast. A number of approaches have been investigated since 2002, such as thermally assisted switching [TAS]  and spin transfer torque [STT] [6, 7]. However all of them suffer from either high power or stability issue and cannot meet the requirements for wide applications. Thermally assisted spin transfer torque [TAS + STT] is an emerging approach [8, 9], which is based on the temperature dependence of exchange bias storage principle , as used in TAS . This switching mechanism involves applying a low current through STT to raise the MTJ temperature above the blocking temperature (T b ) of the antiferromagnetic layer associated to the storage layer, resulting in a hysteresis loop centred about zero (see Figure 1). T b depends mainly on the material composition (e.g. ~423K for IrMn and ~573K for PtMn). This method combines the advantages of both TAS and STT technologies, giving the best trade-off among data reliability, power efficiency, speed and density. Unlike other nanodevices , MTJ can be easily integrated with CMOS circuits . Based on hybrid MTJ/CMOS , innovative memory and logic circuits are expected to provide high performance or new functionalities beyond CMOS. A Spice-compatible efficient compact model for MTJ is an essential requirement for the hybrid MTJ/CMOS design and simulation.
Physical model integration
This compact model is based on our previous STT MTJ model, which is composed of two sub-modules representing respectively the sensing and switching operations . For sensing, the MTJ resistance and TMR ratio are calculated to obtain respectively R P and R AP . For switching, the STT critical current, I C , calculation model was implemented to obtain the hysteresis loop margin of storage layer . The present model offers an improvement over the previous work [14–17] as it integrates the temperature evaluation and STT dynamic switching models to describe the TAS + STT switching approach. In order to optimise the simulation speed, one of the most important performances for logic and memory designs, some physical phenomena like the oscillating effects during switching are omitted.
Temperature evaluation model
Spin Transfer Torque (STT) dynamic switching model
where H ani is in-plane uniaxial magnetic anisotropy field, μ 0 M s is saturation field in the storage layer, α is Gilbert damping coefficient, γ 0 is the gyromagnetic constant, Vol is the volume of storage layer and k B is the Boltzmann constant.
Compact model simulation and validation
Co-simulation of Hybrid MTJ/CMOS circuit
Power and die area estimation
The silicon area of this hybrid circuit is ~9.8 um2 as the width of NMOS transistors is set to 1 μm to provide I switch much higher than I C and reduce the duration down to some nanoseconds. The whole switching operation of TAS + STT between the P and AP states dissipates ~2.7pJ of energy.
In this paper, we present the first compact model for MTJ nanopillar switching using the TAS+STT approach. Transient simulations of a hybrid MTJ/CMOS circuit validate its functionalities and demonstrate that it can be useful to calculate the critical circuit performances like speed, power and die area. The easy parameter interface of the Verilog-A language allows us to analyse the characteristics of MTJ with different materials, area and thin film thickness etc. By using this model, a number of hybrid MTJ/CMOS complex circuits are under investigation in our laboratory.
The authors wish to acknowledge support from the French national projects CILOMAG, ANR-SPIN and NANO2012 project with STMicroelectronics.
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