Fabrication of ultrahigh-density nanowires by electrochemical nanolithography
© Chen et al; licensee Springer. 2011
Received: 28 March 2011
Accepted: 11 July 2011
Published: 11 July 2011
An approach has been developed to produce silver nanoparticles (AgNPs) rapidly on semiconductor wafers using electrochemical deposition. The closely packed AgNPs have a density of up to 1.4 × 1011 cm-2 with good size uniformity. AgNPs retain their shape and position on the substrate when used as nanomasks for producing ultrahigh-density vertical nanowire arrays with controllable size, making it a one-step nanolithography technique. We demonstrate this method on Si/SiGe multilayer superlattices using electrochemical nanopatterning and plasma etching to obtain high-density Si/SiGe multilayer superlattice nanowires.
Low-dimensional systems are of high interest because their unique properties can improve device performance in a range of applications, including optics [1, 2], mechanics , microelectronics , and magnetics . These systems have enhanced surface and quantum confinement effects caused by the large surface-to-volume ratio and small size, making them dramatically different from their bulk counterparts. Superlattice nanowires have the potential to improve the performance of thermoelectronics [6–9], small sizes have lower thermal conductivity [8, 9], and they can be made at a high density, thus providing improved performance.
Generally, there are two major approaches in the fabrication of nanostructures: bottom-up  and top-down . Among the various bottom-up methods, vapor-liquid-solid (VLS) growth is one of the most popular and is used to grow nanostructures such as nanowires [12–14]. VLS growth uses a catalytic liquid-alloy phase that can rapidly adsorb a vapor to supersaturation levels, in which crystal growth can subsequently occur from nucleated seeds at the liquid-solid interface. It is a relatively simple method and yields a large quantity of nanowires from a single growth. However, the requirement of metal particle catalysts risks contaminating the nanowires , and it is not easy to control the density and nanowire size, shape, and crystal orientation simultaneously . Additionally, twin boundaries normally form in the VLS growth, which may affect the subsequent nanowire performance .
Typically, top-down approaches involve lithography, which defines the lateral size and shape of the final structure using an electron/photon-sensitive resist as mask material. Examples are electron beam lithography  and X-ray nanolithography . For example, Zhong et al. have reported ordered SiGe/Si superlattice pillars combining holographic lithography, molecular beam epitaxy (MBE) growth, and wet chemical etching . Although e-beam and X-ray lithographies create uniformly distributed and ordered templates for further top-down processing, they are expensive and time consuming. They also require several processing steps, involving photoresist deposition/removal and chemical or ion beam etching. Other approaches utilize self-assembling  structures such as block copolymers  or anodic aluminum oxide as masks [13, 23]. The outputs of self-assembling techniques are uniform in size and ordered over a large scale; however, they usually require additional deposition, baking, etching, and stripping processes.
Instead of a patterned photoresist, it is also possible to use nanoparticles (NPs) as a nanolithography mask. NPs can be prepared by electrochemical deposition (ECD), an easy, fast, economical, and straightforward way to deposit materials directly on top of semiconductors  or metals [25–27]. To the best of our knowledge, ECD of NPs has not been reported in top-down semiconductor nanostructure fabrication.
We deposit silver nanoparticles (AgNPs) in sizes of tens of nanometers, using pulsed-current driven ECD. By adjusting the deposition conditions, we achieve high-density AgNPs with uniform size and spacing. The resulting one-step electrochemically deposited AgNPs are very robust and can survive further processing. Therefore, they can be used as a hard mask for plasma etching or as a metal-assisted etching mask . By using this mask in combination with chemical vapor deposition (CVD) growth and plasma etching, we are able to fabricate ultrahigh-density (6.2 × 1010 cm-2) Si/SiGe superlattice nanowire arrays over a large area, with individual wires < 30 nm in diameter and approximately 200 nm in length.
The Si/SiGe superlattice wafer is prepared using low-pressure CVD. We grow a ten-period Si/Si0.82Ge0.18 superlattice structure on Si wafers (Si(001), p-type, nominal doping density of 1015 cm-3), and cap the superlattice with Si (Figure 1b). The layer thickness is 10.8 nm for Si and 7.0 nm for the SiGe alloy, as confirmed by X-ray diffraction (XRD, PANalytical X'Pert MRD, PANalytical, Inc., Westborough, MA, USA). Both layers are grown at 580°C, with silane and germane as precursors. The root mean square surface roughness measured by atomic force microscopy (AFM Digital Instrument Nanoscope IV, Veeco Instruments, Santa Barbara, CA, USA) after CVD growth of all the layers is 0.7 nm.
Before performing ECD, we dip the as-grown superlattice wafer in hydrofluoric acid to remove the native oxide on the top Si layer. After rinsing in deionized water (DI) for 5 min, we quickly immerse it into the AgNO3 solution (1 × 10-4 M).
We use pulsed current as the deposition driving force to deposit nanoparticles because this approach is very controllable when depositing a small amount of material. The pulsed signal consists of a long period (T) with a short pulse length (τ). Various immersion times (t) and pulse lengths (τ = 1 ms to 0.5 s) were tried in the experiment in order to obtain AgNPs with uniform small size and high density.
After AgNP deposition, plasma etching is performed to produce superlattice nanowires. The substrate, with the AgNPs acting as a hard mask, is etched by a high-density helicon plasma tool equipped with a diode laser interferometer for in situ etch depth measurement (Figure 1d) . A gas mixture of SF6/C2H2F4 is used. Source power and bias voltage are finely tuned to obtain a vertical etch profile. Using this system, we are able to etch out nanowires up to several microns in length .
Results and discussion
For a much shorter pulse length, τ = 1 ms, the general trend of size distribution is the same, but particles are much smaller and the uniform size distribution lasts to longer immersion times. For comparison, the results of the 50-s immersion time are shown in Figure 2f.
The applied electric field is the driving force of the Ag+ reduction reaction. Each positive pulse applied on the electrode drives Ag+ ions towards the cathode, here the Si surface. The pulse length of the pulse determines the number of adatoms arriving on the surface. Because the applied voltage (20 V) is much higher than the overpotential (300 mV), the effects of the space charge layer and the Helmholtz layer can be ignored when considering the potential profile across the substrate/solution interface .
Low ion concentration or long immersion time can cause a transition from weak interparticle interaction to strong interaction. At long immersion times (t > 40 s in our experiment), depletion layers at adjacent particles merge to create an approximately planar diffusion layer across the entire surface (Figure 3b); this strong interparticle interaction makes the flux of ions per unit area on the surface more uniform. Because the nucleation density is locally variable, densely nucleated regions are therefore expected to have a slower growth rate than regions of the same size but encompassing a smaller number of nanoparticles. Thus, when the immersion time reaches 50 s the size distribution becomes less uniform (Figure 2e). At the same time, Ostwald ripening decreases particle size uniformity as smaller islands are eliminated by the larger ones .
By reducing the pulse length, we achieve higher particle density and smaller particle size while still maintaining good size uniformity. In Figure 2f, the AgNPs have a density of 1.4 × 1011 cm-2, which is almost twice the density for τ = 0.5 s (Figure 2e), while the relative standard deviation of size is only 42%.
where n/s 0 is the particle density on the SEM image area.
Using high-resolution transmission electron microscopy (HRTEM, Philips, CM200UT, Philips Electron Optics BV, Eindhoven, The Netherlands), we can explore the layered structure of the nanowires. Figure 5c, a relatively low-magnification image, shows the periodic variation in brightness representative of the layers. The darker regions are the SiGe alloy because Ge scatters electrons more strongly. We can clearly see the interfaces between Si and SiGe layers. Figure 5d demonstrates that the nanowires are single crystals, as we expect from the MBE growth. In the VLS growth of nanowires, normally twin boundaries are observed . With our method, this problem is eliminated because the starting material is a CVD-grown single-crystalline 2D superlattice.
The SiGe alloy etches faster than pure Si in a SF6/C2H2F4 plasma, giving the edge of the wire a scalloped appearance, effectively introducing surface roughness to the sidewall. The etching process does not affect the crystallographic properties of the superlattice. The surface roughness may result in enhanced phonon scattering .
Si and Ge nanowires have been considered as potentially good thermoelectric materials, because of the reduced thermal conductivity at small dimensions. Superlattice nanowires have even greater potential because of the band offset between Si and SiGe . Thus, electric conductivity is possibly improved through the superlattice structure [38, 39]. The combination of excellent superlattice with edge roughness of our etched nanowires may therefore bring higher thermoelectric efficiency for group IV materials than has been possible so far.
In this paper, we introduce a one-step nanolithography method to fabricate quantum wires with diameters down to 15 nm using electrochemically deposited AgNPs. The AgNP density obtained is as high as 1.4 × 1011 cm-2 with coverage up to 37% over a large area. By adjusting the pulse length and immersion time, the size and density of AgNPs can be well controlled. We demonstrate that these high-density AgNPs can be used as a hard etching mask to fabricate vertically aligned Si/SiGe superlattice nanowires. Because the method does not need lithography to define the pattern, it is much less expensive and can make very small patterns that may have considerable use even if the pattern is not totally uniform. The size and coverage of etched nanostructures only depend on the AgNPs. The method can be used with substrates of any material as long as it conducts sufficiently to form a cathode for the electrochemical process, and a proper etch chemistry to which Ag is resistant is available. The AgNP mask can be used in both metal-assisted etching to etch Si and SiGe and RIE to etch most other semiconductor materials. The method has the potential to make nanowires of different materials, as well as different orientations. It should be very useful in making devices requiring nanowires, such as nanothermoelectronic devices, that require a small size, narrow dispersion, and high density.
We are grateful to F. Flack for reading the manuscript. This research was supported by DOE-BES, grant no. DE-FG02-03ER46028, except as detailed below. FC was partially supported by the Chinese Scholarship Council (CSC). AMK was supported by a SMART Fellowship. Etching (YHT and EAW) was supported by NSF/MRSEC, grant no. DMR-0520527. Facilities support from NSF/MRSEC is acknowledged.
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