Nano-embossing technology on ferroelectric thin film Pb(Zr0.3,Ti0.7)O3 for multi-bit storage application
© Shen et al; licensee Springer. 2011
Received: 24 December 2010
Accepted: 27 July 2011
Published: 27 July 2011
In this work, we apply nano-embossing technique to form a stagger structure in ferroelectric lead zirconate titanate [Pb(Zr0.3, Ti0.7)O3 (PZT)] films and investigate the ferroelectric and electrical characterizations of the embossed and un-embossed regions, respectively, of the same films by using piezoresponse force microscopy (PFM) and Radiant Technologies Precision Material Analyzer. Attributed to the different layer thickness of the patterned ferroelectric thin film, two distinctive coercive voltages have been obtained, thereby, allowing for a single ferroelectric memory cell to contain more than one bit of data.
The development of miniaturized ferroelectric field effect transistors (FeFETs) and random access memories (FeRAMs) [1, 2] has called for fabrication of high-quality ferroelectric nanostructures. How to retain excellent ferroelectricity in nanoscale patterned structures posts a great challenge, as the small thickness of ultra thin films as well as the damages and defects introduced by the conventional photo lithography [3–6] could drastically degrade the ferroelectric properties. Better controlling the quality of the ultra-thin ferroelectric films and alternative patterning techniques are, therefore, highly required.
It is widely understood that multi-bit operation could be one of the most efficient approaches to increase storage densities. In recent years, a great deal of efforts has been made on realizing multi-value storage through circuit design. One of the drawbacks is the additional budget of densities in circuit integration. There have been rarely reports on the research tackling the improvement of fabrication processes and device structures. Nano-embossing technology has emerged as a fast and cost effective technique suitable for patterning structures with feature size down to 20 nm, well below the limit of other lithography techniques used for mass production [7–11]. In this article, we report our initial progress in developing a nano-embossing technique to achieve large arrays of ferroelectric PZT cells, which have potential application in multi-bit storage based on ferroelectric nanostructures.
Since the principle of FeRAM is based on the polarization reversal by an externally applied electric field of metal-ferroelectric-metal capacitors, the computational '0'and '1' are represented by the nonvolatile storage of the negative or positive remnant polarization state, respectively . The ferroelectric films with different thickness need different coercive voltages. A staggered structure with two distinct thickness layers on a PZT thin film can be readily created by a one-step embossing process. In principle, the thinner layer should give rise to the lower switch voltage and the thicker layer to the higher switch voltage . The voltage magnitude corresponds to one of the two polarization charge levels stored in the ferroelectric memory cell. In this way, multiple bits of data can be obtained from a single ferroelectric memory cell by applying different voltages.
Scanning atomic force microscopy (AFM) was used to study the morphology of the embossed arrays, whereas the PFM, which is proved to be one of the most effective method for the nanoscale study and control of ferroelectric domains in bulk crystals and thin films [14, 15], was applied for the study of polarization switching behavior of patterned regions on a PZT film. A Radiant Technologies Precision Material Analyzer was also used for electrical characterizations. The same measurements were also performed on un-patterned regions for comparison.
Results and discussion
In summary, we have successfully demonstrated a new method to fabricate multi-bit memory devices by embossing on thin PZT films at room temperature to form a stagger structure. More than one bit of data is obtained from a single ferroelectric memory cell with such a stagger configuration. Our process has the advantages of high throughput and low cost with a prospect for fabricating multi-bit memory devices by the developed embossing technique.
Ferroelectric PZT thin films were prepared on Pt/Ti/SiO2/Si substrates by the sol-gel method. The raw materials were lead acetate trihydrate [Pb(OCOCH3)2.3H2O, 99.5%], zirconium tetra n-propoxide (Zr(OC3H8)4, 70%), titanium (IV) butoxide (Ti(OC4H9)4, 98%) as precursor material and Methanol/Acetic acid mixed solvent as a solvent. Figure 1a illustrates the embossing process of the PZT film. After spin-on, the precursor film was first baked on hotplate at 60°C in air for 5 min. Then, an embossing process was carried out at room temperature under a pressure of 9 Mpa for 15 min using a silicon template, which has a grating 500 nm lines/spaces. The template used was first coated with an anti-stick layer on its surface in order to reduce its adhesion to the embossed gels and make it easier in later de-mold procedure. After embossing, the gel layers were first pyrolyzed in air on a hotplate at 350°C for 5 min and then crystallized by conventional thermal annealing in air at 650°C for 15 min.
The PFM measurements of ferroelectric characteristics of structured PZT films were carried out at room temperature by a commercial multimode AFM with a Pt coated cantilever (force constant 0.03 to 0.2 N/m, and resonant frequency 14 to 28 kHz). An ac voltage of 1 V and frequency about 200 kHz was applied to measure the in-field nanoscale hysteresis loops.
Further electrical characterization of the embossed and un-embossed PZT ferroelectric films were performed using a Radiant Technologies Precision Material Analyzer with a triangular wave form at 1 kHz after forming Au/Cr electrode pads (100 × 100 μm square) on the films (Figure 3a).
atomic force microscopy
ferroelectric field effect transistors
ferroelectric random access memories
piezoresponse force microscopy.
This work was financially supported by National Basic Research Program of China (2011CBA00603) and the 985" Micro/nanoelectronics Science and Technology Innovation Platform at Fudan University.
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