Copper-selective electrochemical filling of macropore arrays for through-silicon via applications
© Defforge et al.; licensee Springer. 2012
Received: 24 April 2012
Accepted: 12 June 2012
Published: 9 July 2012
In this article, the physico-chemical and electrochemical conditions of through-silicon via formation were studied. First, macropore arrays were etched through a low doped n-type silicon wafer by anodization under illumination into a hydrofluoric acid-based electrolyte. After electrochemical etching, ‘almost’ through-silicon macropores were locally opened by a backside photolithographic process followed by anisotropic etching. The 450 × 450-μm² opened areas were then selectively filled with copper by a potentiostatic electrochemical deposition. Using this process, high density conductive via (4.5 × 105 cm−²) was carried out. The conductive paths were then electrically characterized, and a resistance equal to 32 mΩ/copper-filled macropore was determined.
KeywordsSilicon electrochemical etching Macropore arrays Copper electrochemical deposition Through-silicon via
Nowadays, the scaling down (known as ‘More Moore’) of devices is coming to an end. To maintain a constant evolution of the device performances in the future, alternative ways must be explored. The main one is the device functional diversification and the three-dimensional (3D) integration (‘More than Moore’). The 3D integration is based on the use of the semiconductor volume to connect both sides of a silicon wafer [1, 2]. This technique enables the stacking of the dies and leads to an important surface gain. The through-silicon via (TSV) technology is the key parameter for 3D integration allowing through-silicon connections. This technique is based on the etching of TSV and then the filling of these through holes by a conductive metallic material such as copper or tungsten .
The TSV are usually etched into the silicon using deep reactive ion etching (DRIE) [3, 4]. This technique requires both chemical and physical silicon attacks  to achieve anisotropic etching of silicon. The Bosch process  is often employed to reach high aspect ratio (HAR) structures. It consists of the alternative insertion into the etching chamber of two gaseous species: an etching one (e.g., SF6) and a polymerizing one that immunizes the sidewalls from the SF6 attack. This enables the formation of versatile structures into the silicon wafer. Despite its high versatility, DRIE technique suffers of several limitations. The first limitation is the value of the via aspect ratio that can be attained. Indeed, this value is limited to around 30 or 40 because of homogeneity defects . Furthermore, the main issue of DRIE is the corrugation (or scalloping) development on the silicon sidewalls. This corrugation is directly imputed to the alternative steps of the Bosch etching process. The scalloping is known to be responsible for deposition conformity defaults.
The electrochemical etching of silicon leading to porous silicon formation is an alternative to DRIE for low-cost TSV fabrication. Indeed, macropore formation (pore diameter > 50 nm and most of the time > 1 μm) presents several advantages as compared with dry etching technique. In this case, the wafers are immersed into a HF-based solution (often mixed with solvents and/or surfactants) and an anodic current (or potential) is applied to the sample. The morphology of porous silicon is influenced by the substrate nature (its orientation, doping type, and concentration), the electrolyte composition (HF and additive concentrations), and the anodization parameters (applied current or potential, illumination, etc.) . To obtain HAR, high-density TSV, a low-doped (ρ > 0.5 Ω cm) n-type (100)-oriented substrate can be employed. For example, HAR macropores (aspect ratios can reach 250 to 300)  with ultra-high densities (>108 pores/cm²)  can be achieved homogeneously on 6-in. wafers . These values are much higher than those reached by DRIE and very promising for the future TSV density increasing needs.
Most of the time, TSV are filled with copper because this metal owns one of the highest electrical conductivity. Copper thin films are often obtained by electrochemical deposition. This technique is a low-cost way to achieve large area, high conductivity copper layers. Copper electrochemical deposition into through holes is thus studied for almost two decades because conformal deposition into confined media is much more difficult than on flat surfaces . The chemistry of the electrolyte needs to be adapted to this constraint. Thus, several additives are commonly added to the H2SO4-CuSO4 electrolytic mixture during the copper deposition to ensure void-free, high conductivity copper filling even into HAR structures .
The first part of the present paper describes the different strategies to achieve conductive TSV from ordered macroporous silicon. Then, the conditions of HAR macropore array etching by silicon anodization were developed. After anodization, ‘almost’ through-silicon macropores were locally opened by backside photolithography. The through-silicon macropores were then filled with copper. Finally, these TSV were electrically characterized to determine the resistance of the conductive paths.
Different strategies of conductive through-silicon via localization
Macropore array electrochemical etching
To perform ordered macropore arrays, low phosphorus-doped (ρ = 26 to 33 Ω cm), (100)- oriented silicon was employed. The thickness of the wafers was 240 μm. Highly ordered macropore growth was ensured after inverted micro-pyramid array etching through an oxide mask using photolithography followed by alkaline etching (e.g., immersion into 20 wt.% of KOH solution at 80 °C until complete development of the pyramid). The samples were then anodized under galvanostatic control using a Bio-Logic® SP-150 (Bio-logic Science Instruments, Claix, France). During the anodization, the silicon samples were immersed into a HF (5 wt.%)-ethanol (20 wt.%) mixture maintained at ambient temperature. A 130-W backside illumination of the sample was also essential to photo-generate holes into the semiconductor. Anodization was stopped just before the backside opening; in the present case, approximately 220-μm deep macropores were etched (Figure 4a). The silicon electrochemical etching enabled the formation of 15-μm pitch, 12-μm diameter, with an aspect ratio of 18- to 20-almost-through macropore arrays. For this purpose, the current density was maintained equal to 14.5 mA cm−² during 4 h. This value ensures homogeneous macropore growth and porosity around 70 %.
Copper electrochemical deposition
The copper filling was performed under potentiostatic control (−0.15 V vs. saturated calomel electrode reference) during 6 h to ensure a complete pore filling. The samples were then rinsed with deionized water, polished, and analyzed by SEM and optical microscope.
Results and discussion
Electrical characterization of TSV
After the determination of the different strategies to fabricate local TSV from macropore arrays, the selective opening of almost through-silicon macropores was chosen. Using a simple photolithography step, this technique enabled the local formation of highly conductive TSV. Macropores of 15-μm pitch and 12-μm wide were, thus, etched into a HF-based solution and then selectively filled with copper by a potentiostatic deposition technique during 6 h. During the deposition step, the electrolyte composition must be optimized to ensure void-free copper growth. Then, for the first time, the via resistivity was measured in a low-cost, full electrochemical (etching and filling) TSV fabrication process. The electrical characterizations demonstrated a low resistance of the conductive paths (32 mΩ/via). These values are coherent with the copper theoretical resistivity and explained by the slow copper growth into the macropores. This study proves the feasibility of TSV formation employing electrochemistry for the two main steps of the process (i.e., the pores etching and their filling with conductive material). Indeed, the ordered macropore electrochemical etching technique becomes a viable, low-cost alternative to DRIE for 3D integration.
deep reactive ion etching
high aspect ratio
Janus Green B
polyoxyethylene lauryl ether
scanning electron microscope
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