High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure
© Chen et al.; licensee Springer. 2012
Received: 8 December 2011
Accepted: 26 April 2012
Published: 1 August 2012
A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.
KeywordsGaAs High-k MOSFET Three-dimensional device FinFET
Since the transistor speed in circuit consideration is very impressive, III-V compound semiconductors can be treated as potential channel replacement materials for Si in deep nanoprocess integration. III-V materials such as GaAs and InAs possessing higher electron mobility are expected to conduct higher drive current. Conventionally, operation of III-V field-effect transistors (FETs) mainly relies on a Schottky gate structure to modulate channel potential. However, the Schottky gate suffers from high leakage current issue which restrains III-V devices from very-large-scale integration. Metal-oxide-semiconductor (MOS) gate structure used in Si MOSFET is thermodynamically stable and effective for leakage current reduction. In contrary, the lack of a high-quality oxide/semiconductor scheme has limited the applications of III-V devices for decades. Recently, several groups have demonstrated encouraging results in aspects of III-V surface cleaning or pretreatment methods[2, 3], growth of insulator on various III-V materials[4, 5], as well as realization of III-V MOSFETs[6–11]. Up-to-date III-V MOSFET technologies have demonstrated significant performance enhancement and have achieved low gate leakage[8, 10], high channel mobility[7, 11], and high drive current. Consequently, it is feasible to produce high-performance MOSFETs using III-V materials. On the other hand, when the scaling of planar Si complementary-symmetry metal-oxide-semiconductor (CMOS) gradually approaches its physical limit, three-dimensional fin-shaped FET (FinFET) device architecture[12–15] is a promising alternate enabling transistor scaling beyond the 22-nm technology node. FinFET structure provides superior control of short channel effects; however, there are only few reports on III-V-based FinFETs[15, 17, 18]. In this letter, for the first time, a novel III-V MOSFET device technology based on a three-dimensional FinFET structure is reported. Al2O3 film is used as the gate insulator, and submicron GaAs fin is the channel. Both III-V MOSFET and metal–semiconductor FET (MESFET) with a FinFET structure were fabricated, characterized, and evaluated.
Results and discussion
Electrical performance of 3D III-V nMOSFET and nMESFET with 0.6-μm gate width and 0.5-μm length
2.54 × 105
1.17 × 102
Ion (μA) at VGS = VDS = 1 V
Vth (V) at VDS = 0.1 V
SS (mV/decade) at VDS = 1 V
SS (mV/decade) at VDS = 0.1 V
I on/I off, on current/off current; V GS, gate voltage; V DS, drain voltage; V th, threshold voltage; SS, subthreshold swing; DIBL, drain-induced barrier lowering; MOSFET, metal-oxide-semiconductor field-effect transistor; MESFET, metal–semiconductor field-effect transistor.
Measurement and analysis of high-performance III-V nMOSFET are achieved by applying a FinFET structure to device fabrication. The device exhibits excellent subthreshold characteristics and demonstrates significant performance improvement over conventional Schottky gate nMESFET or planar III-V nMOSFETs because of the enlarging channel width, the existing higher channel electron mobility compared with silicon channel and lower channel interface states, as well as the good gate controllability representing the smaller swing value. The three-dimensional III-V nMOSFET device technology developed illustrates great potential and is promising when the CMOS technology is pushed toward more stringent scaling in the foreseeable future.
SHC is an associate researcher at National Nano Device Laboratories, Hsinchu, 30078, Taiwan. WSL is a full professor in the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. HCY is an assistant professor in the Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, 30401, Taiwan. SJW is an assistant professor in the Department of Materials and Resources Engineering, National Taipei University of Technology, Taipei, 10608, Taiwan. YGL is the vice president of ADATA Technology Company, New Taipei, 23553, Taiwan. HW is a distinguished professor from the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. HSG is a full professor in the Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, People's Republic of China. MCW is a full professor in the Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, 30401, Taiwan.
The authors would like to thank the National Nano Device Laboratories in Hsinchu, Taiwan for the experimental sample preparation.
- International technology Roadmap for Semiconductors, [Online]. Available:http://www.itrs.net/Links/2007TRS/Home2007.htm Available:
- Shahrjerdi D, Garcia-Gutierrez DI, Akyol T, Bank SR, Tutuc E, Lee JC, Banerjee SK: GaAs metal-oxide-semiconductor capacitors using atomic layer deposition of HfO2 gate dielectric: fabrication and characterization. Applied Physics Letters 2007, 91: 193503. 10.1063/1.2806190View Article
- Xuan Y, Lin HC, Ye PD: Simplified surface preparation for GaAs passivation using atomic layer deposited high-k dielectrics. IEEE Trans. Electron Devices 2007, 54(8):1811.View Article
- Ye PD, Wilk GD, Kwo J, Yang B, Gossmann H-JL, Frei M, Chu SNG, Mannaerts JP, Sergent M, Hong M, Ng KK, Bude J: GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition. IEEE Electron Device Letters 2003, 24(4):209.View Article
- Kim HS, Ok I, Zhang M, Lee T, Zhu F, Yu L, Lee JC: Depletion-mode GaAs metal-oxide-semiconductor field-effect transistor with HfO2 dielectric and germanium interfacial passivation layer. Applied Physics Letters 2006, 89: 222904. 10.1063/1.2396914View Article
- Xuan Y, Wu YQ, Ye PD: High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm. IEEE Electron Device Letters 2008, 29(4):294.View Article
- Hill RJW, Moran DAJ, Li X, Zhou H, Macintyre D, Thoms S, Asenov A, Zurcher P, Rajagopalan K, Abrokwah J, Droopad R, Passlack M, Thayne IG: Enhancement-mode GaAs MOSFETs with an In0.3 Ga0.7As channel, a mobility of over 5000 cm2/V·s, and transconductance of over 475 μS/μm. IEEE Electron Device Letters 2007, 28(12):1080.View Article
- Lin HC, Yang T, Sharifi H, Kim SK, Xuan Y, Shen T, Mohammadi S, Ye PD: Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric. Applied Physics Letters 2007, 91: 212101. 10.1063/1.2814052View Article
- Zhang J, Kosel TH, Hall DC, Fay P: Fabrication and performance of 0.25-μm gate length depletion-mode GaAs-channel MOSFETs with self-aligned InAlP native oxide gate dielectric. IEEE Electron Device Letters 2008, 29(2):143.View Article
- Cao Y, Zhang J, Kosel TH, Hall DC, Fay P: Microwave-frequency InAlP-oxide/GaAs MOSFETs. In Proceedings of the IEEE CSIC Symposium: November 12–15: San Antonio. IEEE; 2006, 2006: 43–46.
- Xuan Y, Wu YQ, Lin HC, Shen T, Ye PD: Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer deposited Al2O3 as gate dielectric. IEEE Electron Devices Letters 2007, 28(11):935.View Article
- Doyle B, Boyanov B, Datta S, Doczy M, Hareland S, Jin B, Kavalieros J, Linton T, Rios R, Chau R: Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout. In Proceedings of the Symposium on VLSI Technology. Digest of Technical Papers: June 10–12: Hillsboro. IEEE; 2003, 2003: 133–134.
- Lee RTP: Eu-Jin Lim A, Tan KM, Liow TY, Lo GQ, Samudra GS, Chi DZ, Yeo YC: N-channel FinFETs with 25-nm gate length and Schottky-barrier source and drain featuring ytterbium silicide. IEEE Electron Device Letters 2007, 28(2):164.View Article
- Singh N, Agarwal A, Bera LK, Liow TY, Yang R, Rustagi SC, Tung CH, Kumar R, Lo GQ, Balasubramanian N, Kwong D-L: High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Letters 2006, 27(5):383.View Article
- Benedicto M, Galiana B, Molina-Aldareguia JM, Monaghan S, Hurley PK, Cherkaoui K, Vazquez L, Tejedor P: Fabrication of HfO2 patterns by laser interference nanolithography and selective dry etching for III-V CMOS application. Nanoscale Research Letters 2011, 6: 400. 10.1186/1556-276X-6-400View Article
- Liao WS, Wang MC, Hu YM, Chen SH, Chen KM, Liaw YG, Ye C, Wang WF, Zhou D, Wang H, Gu HS: Drive current and hot carrier reliability improvements of high-aspect-ratio n-channel fin-shaped field effect transistor with high-tensile contact etching stop layer. Applied Physics Letters 2011, 99: 173505. 10.1063/1.3657137View Article
- Liu Y, Neophytou N, Klimeck G, Lundstrom MS: Band-structure effects on the performance of III–V ultrathin-body SOI MOSFETs. IEEE Trans Electron Devices 2008, 55(5):1116.View Article
- Kim D, Krishnamohan T, Nishi Y, Saraswat KC: Band to band tunneling limited off state current in ultra-thin body double gate FETs with high mobility materials: III-V, Ge and strained Si/Ge. In Proceedings of the International Conference on SISPAD: September 6–8: Monterey. IEEE; 2006, 2006: 389–392.
- Suh DC, Cho YD, Kim SW, Ko DH, Lee YS, Cho MH, Oh JW: Improved thermal stability of Al2O3/HfO2/Al2O3 high-k gate dielectric stack on GaAs. Applied Physics Letters 2010, 96: 142112. 10.1063/1.3377915View Article
- Liang CL, Wong H, Cheung NW, Sato RN: Parasitic effects of surface states on GaAs MESFET characteristics at liquid-nitrogen temperature. IEEE Trans Electron Devices 1989, 36(9):1858. 10.1109/16.34258View Article
- Xuan Y, Ye PD, Lin HC: Minority-carrier characteristics of InGaAs metal-oxide-semiconductor structures using atomic-layer-deposited Al2O3 gate dielectric. Applied Physics Letters 2006, 89: 132103. 10.1063/1.2357566View Article
- Chau R, Datta S, Doczy M, Doyle B, Jin B, Kavalieros J, Majumdar A, Metz M, Radosavljevic M: Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans on Nanotechnology 2005, 4(2):153. 10.1109/TNANO.2004.842073View Article
- Sze SM: NG KK: Physics of Semiconductor Devices. 3rd edition. Hoboken: Wiley; 2007.
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