Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET
© Tan et al.; licensee Springer. 2012
Received: 29 June 2012
Accepted: 9 August 2012
Published: 19 August 2012
The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.
KeywordsDevice modeling HSPICE Benchmarking MOSFET CNTFET Logic gates
Carbon nanotubes (CNTs) have been proposed as an alternative channel material to silicon (Si), based on their quantum transport properties which, in principle, allow ballistic transport at room temperature. CNT ballistic modeling has been used to assess the performance of the device at the HSPICE circuit level. Device modeling is vital for projecting the practical performance of a CNT transistor as a switching device in integrated circuits (ICs).
We report the potential of a CNT channel through modeling as a substitute to a silicon channel in a scaled metal-oxide-semiconductor field-effect transistor (MOSFET) for logic applications. By scaling the Si transistor and the density of states (DOS) of the CNT, we observe good agreement between CNT and ballistic Si MOSFET in the drain current–voltage (I V) output characteristics. Output current is critical in determining the switching speed of a transistor in logic gates. We show that the output performances of CNT and Si channel devices are similar in the 45-nm node experimental data. However, the modeling results point to significant reduction in drain-induced barrier lowering (DIBL) and related high field effects in the CNT compared to the short-channel nanoscale Si MOSFET at the same output current. We also assess the effect of channel area restructuring on electric field properties as well as the role of the DOS in determining CNT current. Unlike in the Si MOSFET, it is seen that the performance of a CNT channel is enhanced when the source/drain width is minimized rather than the channel length due to gate-to-source/drain parasitic fringe capacitances. MOSFET scaling according to Moore's law is limited by process controllability.
Carbon nanotube and MOSFET modeling
Source and drain capacitance for multiple substrate insulator thickness
Substrate insulator thickness (nm)
C sbor C db(aF)
I ds(μA) at V G = 1 V
If a CNT can achieve the same current as a MOSFET, an identical channel area (AMOS = ACNT) can be maintained by setting the width of the physical space occupied by the CNTFET to be WCNT = AMOS / LCNT. When W = L for the MOSFET, the general channel area can be expressed as A = (kL)2, where k is the scaling factor. As such, a CNT channel with length, 2kL should attain the same current with W = 0.5kL. Thus, if the physical width of the CNT channel is W ≤ 0.5kL, there will not be any area drawback in output current due to the longer L. In fact, the maximum electric field in CNT is halved, giving EmCNT = EmSi / 2, and is significantly reduced as the CNT channel grows longer. For a CNT with L = 60 nm compared to a Si MOSFET with L = 45 nm, the maximum electric field is Em = 0.83 EmSi.
where Cs and Cd are the source and drain capacitance fitting parameters, respectively,[1, 2] that are used to fit the experimental data and Lg is the length of the gate. The sum of Cgd and Cdb gives the intrinsic capacitance Cint.
where GON is the ON-conductance, Vsc is also known as the channel surface potential, EF is the Fermi energy, kB is the Boltzmann constant, T is the temperature, and q is the electric charge. The equation is iteratively solved and hence includes the effect of gate voltage.
Device model specification at V GS = 1 V
Channel length, L
Contact width, Wcontact
Channel width, W
5 × 10−15 m2
5.63 × 10−15 m2
Chiral vector [n,m]
Maximum current, Idmax
Carrier density, Idmax / [d or W]
Gate capacitance, CG
Drain capacitance, Cd
Source capacitance, Cs
Substrate capacitance, Csub
Total terminal capacitance, Cter
Intrinsic capacitance, Cint = Cgd + Cdb
Load capacitance, CL at 1 GHz
Cutoff frequency with 5-μm wire
Drain-induced barrier lowering
2.99 × 104
9.54 × 106
First, MOSFET logic circuits are built based on a 45-nm generic PDK. The MOSFET designs are then compared with carbon-based circuit models that consist of prototype digital gates implemented in HSPICE circuit simulator. These CNTFETs use 45-nm process design rules, namely the minimum contact size. For a fair assessment, both MOSFET and CNTFET are designed to provide similar current strength (≈46 to 50 μA).
A four-probe measurement was carried out at room temperature to extract the resistance characteristics of the carbon nanotube that was used to form the transistor channel. The normalized resistances were 0.495, 0.744, 0.118, and 0.450 MΩ/nm for R2,3, R2,4, R3,4, and R4,5, respectively, where indices indicate Pd contact labels. The diameter of the SWCNT is 1.5 nm. Calculation shows that the 415-nm nanotube resistance is 27.8 kΩ that is almost equal to the theoretical RON = h/q2 = 25.812 kΩ and four times larger than the theoretically lowest quantum resistance of the SWCNT, RON = h/4q2 = 6.5 kΩ.
Though at 415-nm channel length ballistic transport is not preserved in the CNT, it is still only factor 4 larger than the theoretically expected minimum, suggesting that scattering is not extensive. Nevertheless, the model which assumes ballistic transport predicts similar saturation current levels (≈50 μA) for both the 50- and 415-nm channel devices, as illustrated in Figure5. Practically, this suggests that one must have CNT channel lengths below approximately 100 nm or even low contact resistance in order to utilize ballistic transport in them.
Results and discussion
45-nm process propagation delay computation between CNTFET (with and without interconnect) and MOSFET (post-layout simulation)
CNTFET with 45-nm process design guidelines
MOSFET with 45-nm process
Delay without interconnects
Delay with 5-μm interconnect
Delay (post-layout simulation)
Table3 shows the average propagation delay, tp, for logic gates NOT, NAND2, NAND3, NOR2, and NOR3 for CNTFET with and without interconnect in comparison with MOSFET during post-layout simulation. It is found that NAND3 or NOR3 has the largest propagation delay since both of them has multiple fan-in and fan-out each. In the digital logic simulation of CNTFET, we use an average length of 5 μm per fan-out.
We have established that a longer channel CNT is capable of delivering output currents comparable to those from a 45-nm-node Si MOSFET. This is possible due to the preservation of ballistic transport over distances approaching 100 nm and the higher current density of a single CNT forming the channel. Consequently, in the same practical channel area, a CNT allows reduction of short-channel effects as it has a lower Emax, leading to a lower DIBL and off current.
Devices with thicker substrate insulator and smaller source drain contact area give the highest frequency. In addition to that, logic gates NOT, NAND2, NAND3, NOR2, and NOR3 and their corresponding input and output waveforms are given. The interconnect length of cascading logic gates has a profound effect on the signal propagation delay. In the digital logic simulation, the key limiting factor for high-speed CNT-based chips is the interconnect itself. The performance enhancement of these carbon-based material is negligible if the interconnect capacitance is not reduced significantly with transistor feature size. Bundled metallic MWCNTs are seen as a potential candidate to replace copper interconnects as future IC interconnects once the challenges of integrating CNT interconnects onto existing manufacturing processes are met.
We also show that ballistic transport is not maintained in a CNT when contact resistance is large. A good fit to the data output characteristics from a 50-nm CNT channel device is obtained. As mean free path in a CNT is very long, often exceeding 1 μm, the ballistic process plays a predominant role, similar to one discussed extensively by Riyadi and Arora. In fact, they define a new feature, named ballisticity. The truly ballistic transport is possible as channel length approaches zero. In a finite length, there are always finite probabilities of scattering.
MLPT was born in Bukit Mertajam, Penang, Malaysia, in 1981. He received his B. Eng. (electrical-telecommunication) and M. Eng. (electrical) degrees from Universiti Teknologi Malaysia (UTM), Skudai, Malaysia, in 2003 and 2006, respectively. He conducted his postgraduate research in nanoscale MOSFET modeling at the Intel Penang Design Center, Penang, Malaysia. He recently obtained his Ph.D. degree in 2011 at the University of Cambridge, Cambridge, UK. He is a senior lecturer at UTM. His present research interests are in device modeling and circuit simulation of carbon nanotube, graphene nanoribbon, and MOSFET. MLPT is an IEEE member, member of IET (MIET), graduate member of IEM (GRAD IEM), and member of Queens' College. GL was born in Chania, Crete, Greece in 1983. He holds a B. Eng. (computing and robotic systems) degree from the Department of Electric Engineering in Liverpool University and a Ph.D. degree in engineering from the University of Cambridge. His Ph.D. thesis was in the area of fabricating and characterizing single-walled carbon nanotubes and ZnO nanowire transistors and sensors. He has also worked as a researcher at Nokia's Eurolab between 2009 and 2011 and particularly in developing novel sensors as part of Nokia's Nanosensing group. He, as part of Cambridge-M.I.T i-Teams, examines, identifies, and analyzes commercial potentials for an Intelligent Textbook technology, which uses an artificial intelligence engine, with real target customers in relevant industries. At present, GL is interested in pursuing a career that combines technology and analytical expertise, veiled in a business management environment. He is a member of Churchill College. GAJA received his B.Sc. degree in electrical/electronic engineering from Cardiff University, Wales, UK, in 1979 and his Ph.D. degree in electrical/electronic engineering from the University of Cambridge, Cambridge, UK, in 1983. He has held the 1966 Professorship in Engineering with the University of Cambridge since 1998. He currently heads the Electronics, Power and Energy Conversion Group, one of four major research groups within the Electrical Engineering Division of the Cambridge Engineering Faculty. He has worked for 25 years on integrated and discrete electronic devices for power conversion and on the science and technology of carbon-based electronics for 22 years. He has an active research program on the synthesis and electronic applications of carbon nanotubes and other nanoscale materials. He also has research interest in nanomagnetic materials for spin transport devices. He currently sits on the steering committee of the Nokia-Cambridge University Strategic Collaboration on Nanoscience and Nanotechnology and is the head of the Nokia-CU Nanotechnology for Energy Programme. His current research is focused on integrated power conversion circuits. He has previously held faculty positions at the University of Liverpool (Chair in Electrical Engineering), University of Cambridge, and University of Southampton. He has held the UK Royal Academy of Engineering Overseas Research Award at Stanford University, Stanford, CA, USA, and been a Royal Society visitor at the School of Physics, University of Sydney, Sydney, New South Wales, Australia. He has published over 450 journal and conference papers. GAJA was elected a Fellow of the Royal Academy of Engineering in 2004. In 2007, he was awarded the Royal Academy of Engineering Silver Medal ‘for outstanding personal contributions to British engineering.’
MLPT thanks the Ministry of Higher Education Malaysia and the Universiti Teknologi Malaysia (UTM) for the award of advanced study fellowship leading to a Ph.D. degree at the University of Cambridge. This work is partially supported by a New Academic Staff (NAS) research grant (vot no.: R.J130000.7723.4P030) and the UTM Research University Grant (GUP) (vot no.: Q.J130000.2623.05J42). The authors also gratefully acknowledge the suggestions made by anonymous reviewers that have enhanced the quality of the manuscript greatly.
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