# Dot size effects of nanocrystalline germanium on charging dynamics of memory devices

- Ling-Feng Mao
^{1}Email author

**8**:21

**DOI: **10.1186/1556-276X-8-21

© Mao; licensee Springer. 2013

**Received: **27 November 2012

**Accepted: **6 January 2013

**Published: **10 January 2013

## Abstract

The dot size of nanocrystalline germanium (NC Ge) which impacts on the charging dynamics of memory devices has been theoretically investigated. The calculations demonstrate that the charge stored in the NC Ge layer and the charging current at a given oxide voltage depend on the dot size especially on a few nanometers. They have also been found to obey the tendency of initial increase, then saturation, and lastly, decrease with increasing dot size at any given charging time, which is caused by a compromise between the effects of the lowest conduction states and the capacitance of NC Ge layer on the tunneling. The experimental data from literature have also been used to compare and validate the theoretical analysis.

### Keywords

Quantum size Nanocrystalline Tunneling Memory devices 85.30.Tv 85.35.-p 73.63.-b## Background

Memory structures based on Ge nanocrystals (NCs) have received much attention for the next-generation nonvolatile memory devices due to their extended scalability and improved memory performance [1–7]. There are numerous ways of synthesizing Ge NCs. The mean diameter (*d*) of nanocrystalline germanium (NC Ge) using molecular beam epitaxy is uniquely controlled by the nominal thickness (of the deposited amorphous Ge according to the law *d* ≈ *Kt* with *K* ~ 7 using molecular beam epitaxy [1, 2]. Comparison of electron and hole charge dynamics in NC Ge flash memories has been discussed in [3].

As we know, the crystal size of semiconductor less than 100 nm can lead to a larger band gap and a change in dielectric constant. In the former work [8, 9], the effect of silicon grain size on the performance of thin-film transistors has been studied. To explore NC Ge in a memory device, it is worthy to study how the crystal size of NC Ge on charging dynamics works.

## Methods

### Theory

*E*

_{v}) and the energy of the lowest conduction state (

*E*

_{c}) for spherical NCs of diameter

*d*(given in nanometer) are given by the following expression [3]

*d*) of Ge NCs is uniquely controlled by the nominal thickness (

*t*) of the deposited amorphous Ge using molecular beam epitaxy according to the law [1, 2]

*K*~ 7 uses molecular beam epitaxy. The average density of Ge NCs according to the law [1, 2] is

*ε*

_{a-Si}is the relative dielectric constant of amorphous Si. The capacitance of the amorphous Ge layer is

*ε*

_{a-Ge}is the relative dielectric constant of amorphous Ge. When Ge NCs in the deposited amorphous Ge layer is charged with one elementary charge by the tunneling electron, causing a voltage buildup

*V*=

*Q*/

*C*

_{nc-Ge}, hence the amount of energy stored in this layer is

*d*

_{t-ox}is the tunneling oxide layer thickness. On the other hand, the dielectric constant of NC Ge can be obtained as $\epsilon \left(d\right)=1+\left({\epsilon}_{\mathrm{b}}-1\right)/\left(1+{\left(\frac{{d}_{0}}{d}\right)}^{1.1}\right)$[5] (

*ε*

_{b}is the dielectric constant of bulk germanium). The characteristic radius

*d*

_{0}for Ge is 3.5 nm. According to the simple superposition formula, the dielectric constant of NC Ge layer is

*d*

_{1},

*d*

_{2}, and

*d*

_{3}are the thicknesses of the tunneling oxide layer, nc-Ge layer, and control oxide layer, respectively;

*ε*

_{1},

*ε*

_{2}, and

*ε*

_{3}are the thicknesses of the tunneling oxide layer, nc-Ge layer, and control oxide layer, respectively;

*σ*is the area density of the stored charge. The stored charge density can be calculated using

*J*

_{t-ox}and

*J*

_{g}are the tunneling currents through the tunneling oxide and the gate leakage current, respectively. They have been calculated by using the following equation [10]:

where *m*_{z}^{*} is the effective electron mass in the silicon along the tunneling direction; *E*_{f-L} and *E*_{f-R} are the Fermi levels of the left contact and the right contact, respectively. The transmission coefficient can be calculated using transfer matrix method. Thus, the tunneling current through the tunneling oxide layer and the gate leakage current can be calculated.

## Results and discussion

In this letter, the effective electron mass 0.5 *m*_{0} of SiO_{2}, 0.26 *m*_{0} of silicon, 0.23 *m*_{0} of amorphous Si (a-Si), 0.12 *m*_{0} of NC Ge [11], the relative dielectric constant of SiO_{2}, Si, a-Si, and Ge of 3.9, 11.9, 13.5, and 16, respectively have been used in the calculations [12]. The published electron affinities of crystalline silicon, amorphous silicon, SiO_{2}, and Ge are 4.05, 3.93, 0.9, and 4.0 eV, respectively [13]. In all calculations except the comparison between theory and experiment, the initial voltage across the total oxide containing NC Ge layer is 10 V, and the tunneling and control oxide thickness are 4 and 25 nm, respectively.

## Conclusions

In conclusion, the stored charge and the charging current of NC Ge memory devices with the mean diameter of NC Ge being uniquely controlled by the nominal thickness of the deposition of Ge layer using molecular beam epitaxy are initially increased, then saturated and lastly, decreased with increasing dot size. It is caused by a compromise between the effects of the lowest conduction states and the capacitance of NC Ge layer on the tunneling. Theoretical analysis also demonstrates that the voltage across the tunneling oxide layer is initially kept constant, then slowly decreased and lastly, rapidly decreased with charging time. It is worthy of being noted that NC Ge memory devices may suffer from a small charging current, especially on a few nanometers, due to the change in the lowest conduction states and the capacitance of NC Ge layer.

## Authors’ information

LFM received the Ph.D degree in microelectronics and Solid State Electronics from the Peking University, Beijing, People’s Republic of China in 2001. He is a professor in Soochow University. His research activities include modeling and characterization of quantum effects in MOSFETs and semiconductors, quantum devices, and the fabrication and modeling of integrated optic devices.

## Declarations

### Acknowledgment

The author acknowledges the financial support from the National Natural Science Foundation of China under grant number 61076102 and Natural Science Foundation of Jiangsu Province under grant number BK2012614.

## Authors’ Affiliations

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