Open Access

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

  • Mu-Shih Yeh1,
  • Yung-Chun Wu1Email author,
  • Min-Feng Hung1,
  • Kuan-Cheng Liu1,
  • Yi-Ruei Jhan1,
  • Lun-Chun Chen2 and
  • Chun-Yen Chang2
Nanoscale Research Letters20138:331

DOI: 10.1186/1556-276X-8-331

Received: 5 June 2013

Accepted: 10 July 2013

Published: 22 July 2013


This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.


Twin poly-Si FinFET TFT Nonvolatile memory Ω-gate Nanowires Three-dimensional Flash memory


Electrically erasable programmable read-only memory (EEPROM), which is a kind of nonvolatile memory (NVM) [1, 2], has been widely used in portable products owing to its high density and low cost [3]. Embedded EEPROM that is based on poly-Si thin film transistor (TFT) has attracted much attention because it can meet the low-temperature process requirement in thin film transistor liquid crystal display applications [4, 5]. However, since the process and physical limitations of the device limit the scaling of the flash NVM that is based on a single-crystalline Si substrate, according to Moore’s law, the three-dimensional (3D) multi-layer stack memory provides a high-density flash memory solution. The poly-Si-based NVM also has great potential for realizing 3D high-density multi-layer stack memory [68]. A planar EEPROM that uses twin poly-Si TFTs has also been developed for the above aforementioned applications [4, 9]. The advantages of this twin TFT structure include processing identical to that of a conventional TFT, which is easily embedded on Si wafer, glass, and flexible substrates. Additionally, the low program/erase (P/E) operating voltage of this planar NVM can be easily obtained by increasing the artificial gate coupling ratio (αG).

Recently, several investigations have demonstrated that gate control can be substantially enhanced by introducing a multi-gate with a nanowire (NW) structure [1012]. In our previous works [13, 14], NWs were introduced into twin poly-Si TFT NVM to increase P/E speed. However, reducing the P/E voltage while ensuring the reliability of this device remains a challenge.

Therefore, in this work, to reduce the P/E voltage, we try to use p-channel devices with band-to-band tunneling-induced hot electron (BBHE) operation compared with Fowler-Nordheim (FN) operation and use a Ω-gate structure to have little deterioration. These p-channel twin fin field-effect transistor (FinFET) EEPROM devices with a Ω-gate structure have excellent retention and endurance.


First, a p-type undoped channel twin poly-Si TFT EEPROM with ten NWs was fabricated. Figure 1a presents the structure of the NW twin poly-Si TFT EEPROM. The gate electrodes of two TFTs are connected to form the floating gate, while the source and drain of the larger TFT (T2) are connected to form the control gate. Figure 1b presents the transmission electron microscopy (TEM) image of the NW EEPROM perpendicular to the gate direction; the NWs are surrounded by the gate electrode as a Ω-gate structure with an effective width of 113 nm.
Figure 1

Schematic, TEM image, and equivalent circuit of twin poly-Si TFT EEPROM. (a) Schematic of the twin poly-Si TFT EEPROM cell with ten NWs. (b) The TEM image of Ω-gate NW twin poly-Si TFT EEPROM. The effective channel width is 113 nm × 10 [(61 nm + 16 nm × 2 + 10 nm × 2) × 10)]. (c) The equivalent circuit of twin poly-Si TFT EEPROM.

These devices were fabricated by initially growing a 400-nm-thick thermal oxide layer on 6-in. silicon wafers as substrates. A thin 50-nm-thick undoped amorphous Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. The deposited a-Si layer was then solid-phase-crystallized at 600°C for 24 h in nitrogen ambient. The device’s active NWs were patterned by electron beam (e-beam) direct writing and transferred by reactive-ion etching (RIE). Then, they were dipped into HF solution for 60 s to form the Ω-shaped structure. For gate dielectric, a 15-nm-thick layer of thermal oxide was grown as tunneling oxide. Then, a 150-nm-thick poly-Si layer was deposited and transferred to a floating gate by electron beam direct writing and RIE. Then, the T1 and T2 self-aligned P+ source/drain and gate regions were formed by the implantation of BF2 ions at a dose of 5 × 1015 cm−2. The dopant was activated by ultrarapid thermal annealing at 1,000°C for 1 s in nitrogen ambient. Then, a 200-nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD. Next, the contact holes were defined and 300-nm-thick AlSiCu metallization was performed. Finally, the devices were then sintered at 400°C in nitrogen ambient for 30 min.

In programming, the electrons tunnel into T1 through the tunneling oxide. The tunneling oxide of NW-based EEPROM is surrounded by the gate electrode (Figure 1b). Figure 1c shows the equivalent circuit of this twin TFT NVM:
V FG = C 2 / C 1 + C 2 × V G = W 2 / W 1 + W 2 × V G = α G × V G .

To maximize the voltage drop in the tunnel oxide of T1, the gate capacitance of T2 (C2) must exceed the gate capacitance of T1 (C1). Hence, the NVM device with a high αG exhibits a high P/E speed and can be operated at a low voltage. In this work, the devices were designed to have a coupling ratio of 0.85, which is extremely high for memory applications.

Results and discussion

The TEM image in Figure 1b shows the rounded corners of the twin TFT device structure. First, the NW tri-gated structure, formed by e-beam lithography, was dipped into DHF solution, forming rounded corners. Then, thermal oxidation was performed to form the tunneling oxide; the junction of the channel and the tunneling oxide exhibits some rounding, protecting the tunneling oxide against excessive damage when it is written and erased. The P/E speed and reliability are balanced by Ω-gate formation. By technology computer-aided design (TCAD) simulation, Figure 2 shows the electric field of NWs using tri-gate and Ω-gate structures. The result indicates that the Ω-gate structure has more programming sites around the NWs than the tri-gate structure which are only at the upper corners and that the Ω-gate structure also has smoother electric field.
Figure 2

Electric field of NWs. By TCAD simulation, cut from the AA’ line in the (a) schematic, the electric field around the NWs of (b) tri-gate and (c) Ω-gate structures is shown.

Figure 3 compares the P/E speed of the BBHE operation with that of the FN operation. The device was programmed by FN injection at Vgs = 17 V and by BBHE injection at Vgs = 7 V with Vds = −10 V. The BBHE operation exhibits higher programming speed than the FN operation.
Figure 3

Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.

Figure 4a shows the twin poly-Si TFT-based (Weff/W2/L = 113 nm × 10/6 μm/10 μm) EEPROM P/E cycling endurance characteristics by FN and BBHE, respectively, using the same input voltage. As the number of P/E cycles increased, the magnitude of the memory window disappeared. The floating-gate memory device maintained a wide threshold voltage window of 3.5 V (72.2%) after 104 P/E cycles for FN operation. For BBHE operation, the memory window was almost closed after 104 P/E cycles. Figure 4b shows high-temperature (85°C) retention characteristics of NW-based (Weff/W2/L = 113 nm × 10/6 μm/10 μm) EEPROMs. This figure reveals that after 10 years, the memory window was still 2.2 V when using FN operation. For BBHE operation, the device exhibited almost no data retention capacity. The Ω-gate structure has a higher P/E efficiency than the tri-gate structure because the four corners of the channel are all surrounded by the gate structure [13, 14]. The Ω-gate structure contributes to the equal sharing of the electric field and reduces the probability of leakage in the floating-gate devices in the form of stress-induced leakage current, improving the reliability of the device. Also, the extra corners improve the P/E speed.
Figure 4

Endurance and retention characteristics. (a) Endurance characteristics of the twin poly-Si TFT EEPROM by FN and BBHE. (b) Retention characteristics of the twin poly-Si TFT EEPROM at 85°C by FN and BBHE.

Figure 5 displays a TCAD simulation of FN and BBHE operations. The result indicates that the FN operation produces a high average electric field in the tunneling oxide from the source to the drain, programmed by the tunneling effect. FN operation indicates the average wearing of electric field on the tunneling oxide. BBHE operation produces a sudden electric field peak at the source side, programmed using hot electrons with high energy, causing considerable local damage to the tunneling oxide. This result of consistent P/E that is caused by FN operation reveals better endurance and retention than the BBHE operation for floating-gate devices.
Figure 5

TCAD simulation. (a) FN programming. VFG = VCG × αG = 14.9 V. (b) BBHE programming. VFG = VCG × αG = 5.95 V. Both use the same voltage drop. (c) Electric field comparison of FN and BBHE programming.


This work developed a novel Ω-gate NW-based twin poly-Si TFT EEPROM. Experimental results demonstrated that the Ω-gate NW-based structure had a large memory window and high P/E efficiency because of its multi-gate structure and even oxide electrical field at the NW corners. After 104 P/E cycles, ΔVth = 3.5 V (72.2%). The proposed twin-TFT EEPROM with a fully overlapped control gate exhibited good data endurance and maintained a wide threshold voltage window even after 104 P/E cycles. This Ω-gate NW-based twin poly-Si TFT EEPROM can be easily incorporated into an AMLCD array press and SOI CMOS technology without any additional processing.



The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under contract no. NSC 101-2221-E-007-088-MY2. The National Nano Device Laboratories is greatly appreciated for its technical support.

Authors’ Affiliations

Department of Engineering and System Science, National Tsing Hua University
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University


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© Yeh et al.; licensee Springer. 2013

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