A hot hole-programmed and low-temperature-formed SONOS flash memory
© Chang et al.; licensee Springer. 2013
Received: 19 May 2013
Accepted: 23 July 2013
Published: 31 July 2013
In this study, a high-performance Ti x Zr y Si z O flash memory is demonstrated using a sol–gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600°C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 μs with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 106 s with only 5% (at 85°C) and 10% (at 125°C) charge loss. The barrier height of the Ti x Zr y Si z O film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-κ sol–gel film.
KeywordsSol–gel Hole trapping Flash memory
Silicon-oxide-nitride-oxide-silicon (SONOS)-type memory is widely used for nonvolatile memory . Compared to conventional floating-gate memory, SONOS-type memory has the advantage of high date retention, high endurance, and fast program/erase (P/E) speed . However, the primary drawback of this memory type is that a higher voltage (typically >10 V) is required to inject carriers into the charge trapping layer, which results in excessive power consumption and leakage current. A device with low operation voltage is necessary for the development of high-performance memory .
Recently, high-κ materials have been considered as an effective charge storage material to achieve a faster program speed and improved charge retention [4, 5]. Numerous technologies have been developed for the preparation of various high-κ films, including the sol–gel method, atomic layer deposition, physical vapor deposition, and chemical vapor deposition [6–9]. Among them, the sol–gel method is an appealing technique. Using this method, the high-κ film can be easily synthesized by mixing many types of materials in a solvent, followed by a post-anneal process after spin-coating on a substrate . The advantages of the sol–gel method include simplicity, low cost, good uniformity, and compatibility with the current production lines of semiconductor plants . However, performing high-temperature post-annealing to obtain a satisfying high-κ film was unavoidable in previous studies [6, 10–13]. The high-temperature post-annealing, which is typically above 900°C, hinders the wide application of the sol–gel method, such as in thin-film transistors or flexible devices.
In this study, a high-quality Ti x Zr y Si z O film was synthesized using the sol–gel method and low-temperature post-anneal. The sol–gel-derived Ti x Zr y Si z O film was applied as the charge storage layer of the SONOS-type flash memory. Identical to the high-temperature sample, the low-temperature post-annealed memory shows a noteworthy hot hole trapping characteristic and exhibits a lower operation voltage, faster P/E speed, and better data retention than previously demonstrated.
The fabrication of sol–gel-derived memory was started with a local oxidation of silicon isolation process on a p-type (100), 6-in. Si substrate. A 4-nm tunneling oxide was thermally grown at 925°C in a furnace. A sol–gel solution containing zirconium tetrachloride (ZrCl4), silicon tetrachloride (SiCl4), and titanium tetrachloride (TiCl4) was then spin-coated onto the substrate at 3,000 rpm for 60 s at ambient temperature. The sol–gel solution used ethanol as the solvent, and the molar ratio of the mixture for ZrCl4/SiCl4/TiCl4/ethanol was 1:1:1:1,000.
Results and discussion
where Kb, T, a, b, and φ t are the Boltzmann constant, the measurement temperature, a constant that depends on the trap density, a constant that depends on the electric permittivity, and the depth of the trap potential well, respectively.
As shown in Figure 8a, the threshold voltage (Vt) shift increased with increasing operation voltage; therefore, more ‘hot’ holes were generated and injected into the charge storage layer. The maximum memory window can be as large as 8 V. The program speed is 16 μs with a −2-V Vt shift for the program conditions of Vg = −8 V and Vd = 8 V. Compared with the erase speed shown in Figure 8b, only 1.7 μs is required for a 2-V Vt shift. It is reasonable that the erase speed is approximately ten times faster than the program speed because this memory is programmed by BBHH and erased by CHE. Even at only 6-V operation, the P/E speed can be as fast as 120:5.2 μs with a 2-V Vt shift. The fast P/E speed at such low operation voltage is superior to that demonstrated in previous studies [18–20] and is beneficial to the development of high-performance memory. This favorable result is ascribed to the formation of more trapping sites in the Ti x Zr y Si z O film at 600°C annealing, and hence, more carries can be captured in the traps.
Comparison of P/E speed and data retention of the sol–gel-derived high- κ memory devices
This work (Ti x Zr y Si z O with 600°C annealing)
Ti x Zr y Si z O NC with 900°C annealing
Zr x Hf y Si z O NC with 900°C annealing
HfSi x O y with 900°C annealing
Program speed (2-V shift)
1.6 × 10−5 s
2.4 × 10−5 s
3 × 10−5 s
2 × 10−2 s
(Vg = −8 V, Vd = 8 V)
1.2 × 10−4
(Vg = −8 V, Vd = 8 V)
(Vg = 10 V, Vd = 9 V)
(Vg = Vd = 10 V)
(Vg = −6 V, Vd = 6 V)
Erase speed (2-V shift)
1.7 × 10−6 s
1.9 × 10−6 s
2 × 10−3 s
5 × 10−5 s
(Vg = Vd = 8 V)
5.2 × 10−6 s
(Vg = Vd = 8 V)
(Vg = −10 V, Vd = 9 V)
(Vg = −10 V, Vd = 10 V)
(Vg = Vd = 6 V)
Retention at 85°C
(only 104 s)
Retention at 125°C
We demonstrated a high-performance sol–gel-derived Ti x Zr y Si z O memory in this study. The memory exhibits a notable hot hole program characteristic, and hence, a much higher erase speed is achieved. The barrier height for the Ti x Zr y Si z O film to silicon oxide was estimated to be approximately 1.15 eV for hole trapping, using the Poole-Frenkel emission model. Unlike other sol–gel-derived memories that require a higher temperature annealing process, this Ti x Zr y Si z O memory with relatively low-temperature annealing exhibits excellent electrical performance such as low-voltage operation, fast P/E speed, and robust data retention.
Band-band hot hole
Channel hot electron
Rapid thermal annealing
Transmission electron microscopy
X-ray photoelectron spectroscopy.
This work was financially supported by Taipei Medical University and Taipei Medical University Hospital under the contract number 101TMU-TMUH-07.
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