The performance and reliability of metal-oxide semiconductor is significantly influenced by the quality of the grown Si/SiO_{2} interface. The interface trap as a function of energy in the Si band gap exhibits two peaks, 0.25 and 0.85 eV for Si(110)/SiO_{2} interface [1] and 0.31 and 0.84 eV for Si(111)/SiO_{2} interface [2]. The P_{b} center resides on flat surfaces (terraces), not at ledges [3]; it is considered as the main source of defects at the Si(111)/SiO_{2} interface. It was named as P_{b0} with reference to the P_{b1} center on Si(100). The interface defect is amphoteric that is a donor level below mid gap and an acceptor level above mid gap. Memory structures based on nanocrystalline (NC) semiconductor have received much attention for next-generation nonvolatile memory devices due to their extended scalability and improved memory performance [4–6]. Recently, the quantum size effects caused by the channel material NC Si neglecting the interface charge on the threshold voltage of thin-film transistors without float gate [7] and on charging the dynamics of NC memory devices [8] have been studied. Here, both the quantum size effects caused by the float gate material NC and the interface traps effects on the retention time of memory devices are studied.

### Theory

For p-type silicon, Poisson's equation can be written as follows:

$\frac{{\partial}^{2}\psi}{\partial {x}^{2}}=-\frac{q\phantom{\rule{0.5em}{0ex}}}{{\u03f5}_{\mathrm{s}}}\left({N}_{A}\left({e}^{-\frac{\mathit{q\psi}}{\mathit{kT}}}-1\right)-\frac{{n}_{i}^{2}}{{N}_{A}}\left({e}^{\frac{\mathit{q\psi}}{\mathit{kT}}}-1\right)\right)\phantom{\rule{0.5em}{0ex}}$

(1)

where

*φ*(z) is the electrostatic potential,

*ϵ*_{s} is the dielectric constant of silicon,

*N*_{A} is the ionized acceptor concentrations,

*n*_{i} is the intrinsic density,

*k* is the Boltzmann constant, and

*T* is the temperature. Using the relationship

$\frac{\partial}{\partial z}{\left[\frac{\partial \mathit{\phi}}{\partial z}\right]}^{2}=2\frac{\partial \phi}{\partial z}\frac{{\partial}^{2}\phi}{\partial {z}^{2}}$ and then integrating from 0 to

*φ*_{
s
}, obtain surface electric field at the side of silicon substrate as follows:

${E}_{S}=\pm \sqrt{\frac{2\mathit{qkT}{N}_{A}\phantom{\rule{0.5em}{0ex}}}{{\u03f5}_{\mathrm{s}}}\left({e}^{-\frac{q{\psi}_{S}}{\mathit{kT}}}-1+\frac{q{\psi}_{S}}{\mathit{kT}}+\frac{{n}_{i}^{2}}{{\left({N}_{A}\right)}^{2}}\left({e}^{\frac{q{\psi}_{S}}{\mathit{kT}}}-1-\frac{q{\psi}_{S}}{\mathit{kT}}\right)\right)\phantom{\rule{0.25em}{0ex}}}\phantom{\rule{1em}{0ex}}$

(2)

If

*ψ*_{s} > 0, choose the ‘+’ sign (for a p-type semiconductor), and if

*ψ*_{s} < 0, choose the ‘−’ sign. Poisson's equation in the gate oxide and the NC Ge layer with uniformly stored charge density

*Q*_{nc} per unit area can be written as follows:

$\frac{{\partial}^{2}\psi}{\partial {x}^{2}}=0\phantom{\rule{0.75em}{0ex}}$

(3)

$\frac{{\partial}^{2}\psi}{\partial {x}^{2}}=-\frac{{Q}_{\mathrm{nc}}}{{\u03f5}_{\mathrm{nc}}{d}_{\mathrm{nc}}}\phantom{\rule{2.5em}{0ex}}$

(4)

where

*d*_{nc} and

*ϵ*_{nc} are the thickness and the average dielectric constant of NC Ge layer, respectively. Consider boundary conditions for the case of interface charge density

*Q*_{it} captured by the traps at Si/SiO

_{2} interface; thus, the electric field across the tunneling oxide layer is the following:

${E}_{\mathrm{ox}}=-\frac{-{\u03f5}_{S}{E}_{S}+{Q}_{\mathrm{it}}}{{\u03f5}_{\mathrm{ox}}}\phantom{\rule{3.5em}{0ex}}$

(5)

where

*ϵ*_{ox} is the dielectric constant of SiO

_{2}. The applied gate voltage of a NC flash memory device is equal to the sum of the voltage drop across the layer of NC Ge, SiO

_{2}, and p-Si:

$\begin{array}{ll}{V}_{g}=& -{Q}_{\mathrm{nc}}\left(\frac{{d}_{\mathrm{nc}}}{2{\u03f5}_{\mathrm{nc}}}+\frac{{d}_{\mathrm{cox}}}{{\u03f5}_{\mathrm{ox}}}\right)+\left({\u03f5}_{S}{E}_{S}-{Q}_{\mathit{it}}\right)\\ \times \left(\frac{{d}_{\mathrm{tox}}}{{\u03f5}_{\mathrm{ox}}}+\frac{{d}_{\mathrm{nc}}\phantom{\rule{0.25em}{0ex}}}{{\u03f5}_{\mathrm{nc}}}+\frac{{d}_{\mathrm{cox}}}{{\u03f5}_{\mathrm{ox}}}\right)+{\psi}_{S}\phantom{\rule{0.25em}{0ex}}\end{array}$

(6)

where

*d*_{tox} and

*d*_{cox} are the thickness of the tunneling oxide layer and control oxide layer, respectively. The interface charge density is obtained by multiplying the density of interface trap states (

*D*_{it}) by the trap occupation probability and integrating over the bandgap [

9]:

${Q}_{\mathrm{it}}=q{\displaystyle \int {D}_{\mathrm{it}}\left(E\right)F\left(E\right)}\mathit{dE}$

(7)

The Fermi-Dirac distribution function *F*(*E*) for donor interface traps is (1 + 2 exp[(*E*_{
F
} − *E*)/(*kT*)])^{−1} and that for the acceptor interface traps is (1 + 4 exp[(*E* − *E*_{
F
})/(*kT*)])^{−1}.

The leakage current can be calculated using [

10]:

$J={\displaystyle {\int}_{0}^{\infty}\frac{q{m}^{*}\mathit{kT}}{2{\pi}^{2}{\hslash}^{3}}T\left(E\right)ln\left(\frac{1+exp\left(\left({E}_{F}-E\right)/\mathit{kT}\right)}{1+exp\left(\left({E}_{F}-E-\mathit{qV}\right)/\mathit{kT}\right)}\right)\mathit{dE}}$

(8)

where

*T*(

*E*) is the transmission coefficient calculated by solving Equation

8 using the transfer matrix method,

*V* is the voltage drop values in the tunneling region,

*m** is the effective electron mass, and

*ħ* is the reduced Planck constant. The energy of the highest valence state (

*E*_{v}) and the energy of the lowest conduction state (

*E*_{c}) for spherical NCs of the diameter

*d* (given in nanometer) are given by the following expression [

4]:

${E}_{\mathrm{c}}\left(d\right)={E}_{\mathrm{c}}\left(\infty \right)+\frac{11863.7}{{d}^{2}+2.391d+4.252}\phantom{\rule{0.5em}{0ex}}\left(\mathrm{meV}\right)$

(9)

${E}_{\mathrm{v}}\left(d\right)={E}_{\mathrm{v}}\left(\infty \right)-\frac{15143.8}{{d}^{2}+6.465d+2.546}\phantom{\rule{0.5em}{0ex}}\left(\mathrm{meV}\right)$

(10)

The mean diameter (

*d*) of NC Ge is uniquely controlled by the nominal thickness (

*t*) of the deposited amorphous Ge using molecular beam epitaxy according to the law

*d* ≅

*Kt* (K approximately 7), and the average density of NC Ge

*D*_{NC} ≅ 6 × 10

^{
−3
}*/t*^{2}[

5]. Thus, the filling factor that is the ratio of area of NC Ge to total area can be obtained as 0.2349. The size-dependent dielectric constant can be obtained as follows [

6]:

$\u03f5\left(d\right)=1+\left({\u03f5}_{\mathrm{b}}-1\right)/\left(1+{\left(2{d}_{0}/d\right)}^{1.1}\right)$

(11)

where *ϵ*_{b} is dielectric constant of bulk Ge. The characteristic radius for Ge is 3.5 nm. Considering the fill factor, the average dielectric constant of NC Ge layer can be estimated using parallel capacitor treatment.

The top of the valence band of p-type silicon bends upward (*ψ*_{s} < 0 and *Ε*_{s} < 0) which causes an accumulation of majority carriers (holes) near the interface. Thus, the interface traps capture more holes when the float gate has been charged with electrons [9]. It results that the electric field across the tunneling oxide layer increases according to Equation 5, the transmission coefficient through the tunneling oxide layer increases, and the retention time decreases. Whereas, the top of the valence band of n-type silicon bends upward which causes a depletion of majority carriers (electrons) near the interface, and the interface traps capture less holes or capture electrons if the band bends even more so that the Fermi is level below mid gap [9]. Thus, it results that the electric field across the tunneling oxide layer decreases, the transmission coefficient decreases, and the retention time increases. Additionally, such a method is still valid for metal (or other semiconductor) NC memory in just using their equations to substitute Equations 9, 10, and 11 for NC Ge.