Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale
© Ho et al.; licensee Springer. 2013
Received: 9 October 2013
Accepted: 23 November 2013
Published: 1 December 2013
We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.
Silicon nanostructures have unique optical, electrical, and thermoelectric properties not observed in its bulk embodiment. The advantages conferred by these traits have seen Si nanostructures being applied in nanoelectronics for transistor miniaturization [1–3], photovoltaics for exceptional light trapping [4–6], and photodetection for ultrahigh photoresponsivity . Si nanostructures such as Si nanowires (SiNWs) have also enabled ultra-sensitivity to be realized in chemical and biological sensing , efficient thermoelectric performance , enhanced performance in Li-ion batteries , and nanocapacitor arrays .
Successful realization of Si-nanostructured devices on a manufacturing scale, however, requires practical techniques of producing the nanostructures with controlled dimensions, patterns, crystalline structures, and electronic qualities. Metal-assisted chemical etching (MACE) or metal-catalyzed electroless etching (MCEE) is a simple technique first demonstrated by Peng et al., which can be used to generate high aspect ratio Si nanostructures [12, 13]. In this manuscript, this technique is referred to as MCEE because this provides a more explicit description of the process. Sidewall inclination common in reactive ion etching (RIE)  and scalloping effects typical of deep reactive ion etching  are avoided in MCEE. The process does not require the complex precursors used in vapor-liquid-solid growth or chemical vapor deposition, and the expensive equipment of inductive coupled plasma-RIE or DRIE. Properties such as doping level and type, crystal orientation, and quality are determined simply by the starting Si wafers.
Approaches combining nanoscale patterning techniques with MCEE have been reported. The combination allows more control over the order, diameter, and density of the Si nanostructures. This was demonstrated with nanosphere lithography which is based on the self-assembly of a monolayer of nanospheres (e.g., polystyrene  or silica ) into ordered hexagonal close-packed arrays. However, ordering of the nanospheres and the resulting Si nanostructures are limited to domains. Huang et al. employed an anodic aluminum oxide (AAO) template and a Cr/Au evaporation step to define the mask for catalytic etching to form SiNWs . While this is a simple and cost-effective method, the positions of the nanostructures are limited to short-ranged hexagonal arrangements, and large-scale production will likely be hampered by inefficient AAO template transfer to the Si substrate. Lately, block copolymer lithography has been paired with MCEE to produce highly dense Si nanostructure arrays. But a distribution of dimensions exists, and ordered arrangement is limited to small areas .
In order to fabricate Si nanostructures with various array configurations, cross-sectional shapes, and perfect ordering over large areas, interference lithography (IL) in combination with MCEE has been employed by Choi et al. . Si nanostructures with circular or square cross-sections and Si nanofin arrays can be readily obtained by tuning the IL exposure process. This is an attractive lithographic process that can be used to rapidly generate perfectly periodic patterns over large areas. Through this approach, SiNWs of sub-100-nm diameters have been achieved .
Despite the advantages of IL, the density and lateral dimension of Si nanostructures are ultimately limited by the wavelength of the incident light , an issue common with UV and DUV photolithographies. Furthermore, the cross-sectional shapes and array configurations are constrained to those permitted by interference. While advanced nanolithography techniques such as electron beam lithography (EBL) are capable of realizing feature dimensions down to a few nanometers, and are valuable tools in a research environment, they are not amenable to an industrial high-throughput manufacturing setting . These limitations are circumvented with nanoimprint lithography (NIL) in which the mould pattern can be written by EBL and thus have excellent versatility in pattern design and resolution similar to EBL. Wafer-scale patterning can subsequently be achieved by direct large-area nanoimprinting [23, 24] or through a stepper.
Recently, substrate conformal imprint lithography was used in combination with MCEE by Wang et al. to produce ordered arrays of elliptical nanopillars. Unfortunately, the generated nanostructures, of relatively large dimensions (several hundreds of nanometers), do not realize the high resolution potential offered by NIL and also exhibited a high degree of porosity . A combinatory technique consisting of soft lithography, SiN x deposition and etching, and MCEE has also been reported by Balasundaram et al. , but the elaborate procedure negates the simplicity of MCEE.
In this work, we employ a simple two-stage procedure consisting of step-and-repeat nanoimprint lithography (SRNIL)  with etch-resistant NIL resin chemistry, and optimized MCEE conditions to fabricate wafer-scale, near perfectly ordered, single crystalline, non-porous silicon nanostructures with controlled feature sizes down to sub-50 nm. Circular, hexagonal, and rectangular cross-sectional Si nanostructures in hexagonal or square array configurations with 150- or 300-nm periods (corresponding to array packing densities up to 5.13 × 107 structures/mm2) and aspect ratios as high as 20:1 or more were produced using EBL-defined NIL pore-patterned moulds and MCEE. The results clearly illustrate the high resolution potential of NIL and deep-etching capabilities of MCEE. To our knowledge, this is the first demonstration of versatile pattern generation of near perfectly ordered Si nanostructures down to sub-50-nm feature sizes via SRNIL and MCEE on a wafer scale. This offers a simple and fast route towards semiconductor nanostructured device production.
Wafer-scale step-and-repeat nanoimprint lithography
Metal-catalyzed electroless etching
The mechanism of MCEE is well discussed in literature and will not be described at length here . Briefly, in a solution of HF and an oxidative agent, e.g., H2O2, of appropriate concentrations, regions of Si that are in contact with a noble metal, such as Au or Ag, are etched much faster than those regions without metal coverage. This phenomenon arises because the noble metal acts as a catalyst facilitating the local injection of holes into Si, resulting in its oxidation and subsequent removal by HF. The reaction is redox in nature and the metal ‘sinks’ into Si, creating an etched path. Therefore, by pre-patterning a noble metal layer on Si prior to immersion in HF/H2O2, patterned etched structures can be generated.
Results and discussion
Molar concentrations of HF and H2O2, abbreviated as [HF] and [H2O2], respectively, other than that reported in this work (4.6 M HF and 0.44 M H2O2), have been employed in our experiments. However, it is found that 4.6 M HF and 0.44 M H2O2 are optimal for rapidly generating high aspect ratio Si nanostructures with sidewalls of low porosity. Similar concentrations have also been used by other works reported in the literature [18, 20, 21, 29, 30]. The influence of [HF] and [H2O2] in fabricating the Si nanostructures in MCEE has been discussed by Lianto  and Lianto et al. . According to them, the porosity of the etched nanostructures is controlled by the concentration of excess electronic holes in Si. Since the flux and consumption of the electronic holes depend on [H2O2] and [HF], respectively, these are crucial in determining the structure of the etched bodies and the etch rate. Higher [H2O2] is correlated with increased porosity because the flux of the electronic holes injected into Si is higher, and more excess holes can diffuse from the catalyst to cause porosity in other regions of the Si nanostructures. A similar phenomenon has been observed in our experiments and by Wang et al.  where higher [H2O2] leads to increased sidewall roughness and structure porosity. However, even with increased [H2O2], etching occurs much faster in the regions of Si covered by the Au catalyst such that a large degree of anisotropy is maintained, albeit at the expense of greater sidewall roughness and porosity, especially near the top of the Si nanostructures. Conversely, a low [H2O2] is still insufficient to eliminate porosity in the Si nanostructures when [HF] is low, although it allows a slower, more controllable etch rate.
Increasing [HF] can significantly reduce the porosity of the sidewalls, while also increasing the etch rate . Unfortunately, an excessively high [HF] leads to the increased evolution of H2 bubbles which can interfere with the spatial etch uniformity. As aforementioned, 4.6 M HF and 0.44 M H2O2 are chosen as an optimal combination. However, lower concentrations, possibly in similar relative molar ratios, may also be employed to provide a slower etch rate but with minimal porosity for the generation of lower aspect ratio Si nanostructures in MCEE. Hence, depending on the degree of nanoporosity and etch rate required, the concentration of the MCEE solution can be suitably tuned.
Due to the lack of an etch stop layer in MCEE, controlled halting of the wet etching process requires rapid removal of the wafer from the etching solution and subsequent immersion/rinsing in a bath of non-reacting dilution medium (deionized water in this case). This technique quenches the reaction, and good spatial control can be effected provided that the removal and immersion/rinsing steps can be executed in a much shorter time frame (approximately 1 s, in our case) relative to the total etch time. Considering the etch rate of approximately 320 nm/min, etch depths of several hundreds of nanometers to more than a micron can be achieved with low relative spatial etch depth variation, since the absolute difference in spatial etch depth represents only a small fraction of the height of the Si nanostructures. For shallower etch depths, a slower, more controlled etch rate would be recommended and can be achieved by lowering [HF] and [H2O2] but in suitable molar concentration ratios. Large-scale reproducibility in large wafers may require suitable engineering control methods such as large baths of deionized water under constant agitation or rapidly flowing deionized water for quenching of reaction and rinsing.
As shown in the magnified TEM images of Figure 7c,d, the bottom of the Si nanostructure has smoother sidewalls than the top because of shorter exposure to the etching solution, and this is consistent with reports in literature [16, 28]. The selected area electron diffraction (SAED) pattern in Figure 7f is obtained from near the tip of a single nanorod. The sharp and clear SAED pattern is typical of a single-crystal face-centered cubic material like silicon, observed in the (011) beam direction. No stray spots or elongation of spots is observed, indicating that high crystal quality is maintained after the etching. Figure 7 shows that MCEE occurs largely along the <100 > direction away from the top surface of the Si(100) wafer. The observed anisotropy of MCEE in Si is consistent with the reports in literature [16–18, 20, 21, 28, 32, 33] and may be explained by the back-bond breaking theory [33, 34]. Briefly, each atom on the (100) surface has only two back-bonds compared to three for that on the (110) and (111) surfaces, such that the former has a weaker back-bond strength. It is thus more easily removed during MCEE, and the etching occurs preferentially along the <100 > direction.
Our work provides evidence of the controllability of the ordering, shapes, and dimensions of MCEE nanostructures by nanoimprinting, and general anisotropy in MCEE profiles simply by appropriate substrate orientation selection, mask material selection and connectivity of the catalytic layer. Further, by taking advantage of the fact that NIL moulds can be written with arbitrary patterns not necessarily of simple regular or periodic designs, we posit that complex three-dimensional nanostructures [35, 36] with applications in photonics and optoelectronics can similarly be generated on a manufacturing scale for widespread implementation. In fact, through SRNIL, the patterns can be varied across the wafer by employing differently patterned moulds. Other nanoscale patterning techniques, for instance, interference lithography, and short-range self-assembly methods like AAO patterning, block copolymer, and nanosphere lithography are limited to producing periodic arrays of rod or wire-like shapes. Parallel and large-area wafer-scale patterning, as well as repeated use of a single mould, is further afforded by SRNIL. These features make our approach of SRNIL with MCEE more practically useful than other approaches published previously. The realization of long-range ordering of high aspect ratio Si nanostructures at sub-50-nm resolution with the aforementioned pattern versatility and on a wafer scale has not yet been reported.
In conclusion, we demonstrate the versatile pattern generation of wafer-scale, highly uniform, well-ordered Si nanostructures with sub-50-nm resolution using a combination of step-and-repeat nanoimprint lithography and metal-catalyzed electroless etching. The long-range order and variability of nanoscale patterning offered in this approach cannot be achieved by self-organized methods of nanopatterning such as AAO templating, nanosphere lithography, and block copolymer self-assembly. Versatility in nanoimprint mould patterns allows this combinatory method to overcome the shortcomings of interference lithography and yet produce nanoscale features, previously limited to research-scale E-beam lithography or deep UV photolithography, on a wafer scale. The Si nanostructures produced in our approach show a high degree of fidelity as the user-defined SRNIL patterns, and retain non-porous top surfaces due to the substrate adherent, and chemically resistant SRNIL resin mask. This method is capable of producing high aspect ratio structures through a simple inexpensive wet etching setup. Minor lateral sidewall etching which arises from prolonged immersion in the etching solution reduces the dimensions of the Si nanostructures and should be taken into account in the design and fabrication process. Bearing these in mind, our approach could be very useful for large-scale nanostructured device production.
JH and QW are Ph.D. candidates working on nanopatterning, fabrication, and growth of semiconductor nanostructures for photovoltaic and light-emission applications with the National University of Singapore (NUS). JD works on nanolithography and is with the Institute of Materials Research and Engineering (IMRE) of the Agency of Science, Technology and Research (A*STAR) in Singapore. AT is a Professor at the Department of Mechanical Engineering, NUS. SC is a Professor at the Department of Electrical and Computer Engineering, NUS.
Anodic aluminum oxide
Electron beam lithography
Metal-assisted chemical etching
Metal-catalyzed electroless etching
Reactive ion etching
Selected area electron diffraction
Scanning electron microscopy
Step-and-repeat nanoimprint lithography
Transmission electron microscopy.
This work was supported in part by the National University of Singapore (NUS), the Singapore-MIT Alliance (SMA), and the Agency of Science Technology and Research (A*STAR).
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