# Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications

- Meisam Rahmani
^{1}, - Mohammad Taghi Ahmadi
^{1, 2}, - Hediyeh Karimi Feiz Abadi
^{3, 4}, - Mehdi Saeidmanesh
^{1}, - Elnaz Akbari
^{4}and - Razali Ismail
^{1}Email author

**8**:55

**DOI: **10.1186/1556-276X-8-55

© Rahmani et al.; licensee Springer. 2013

**Received: **31 October 2012

**Accepted: **8 January 2013

**Published: **30 January 2013

## Abstract

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si *metal-oxide-semiconductor field-effect transistor* s. The current–voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current–voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

### Keywords

Trilayer graphene nanoribbon (TGN) ABA and ABC stacking TGN Schottky-barrier FET High-speed switch## Background

Graphene, as a single layer of carbon atoms with hexagonal symmetry and different types such as monolayer, bilayer, trilayer, and multilayers, has attracted new research attention. Very high carrier mobility can be achieved from graphene-based materials which makes them a promising candidate for nanoelectronic devices [1, 2]. Recently, electron and hole mobilities of a suspended graphene have reached as high as 2 × 10^{5} cm^{2}/V·s [3]. Also, ballistic transport has been observed at room temperature in these materials [3]. Layers of graphene can be stacked differently depending on the horizontal shift of graphene planes [4, 5]. Every individual multilayer graphene sequence behaves like a new material, and different stacking of graphene sheet lead to different electronic properties [3, 6, 7]. In addition, the configuration of graphene layers plays a significant role to realize either metallic or semiconducting electronic behavior [4, 8, 9].

*y*and

*z*directions, while an analog type in the

*x*direction. It is also remarkable that the electrical property of TGN is a strong function of interlayer stacking sequences [10]. Two well-known forms of TGN with different stacking manners are understood as ABA (Bernal) and ABC (rhombohedral) [11]. The simplest crystallographic structure is hexagonal or AA stacking, where each layer is placed directly on top of another; however, it is unstable. AB (Bernal) stacking is the distinct stacking structure for bilayers. For trilayers, it can be formed as either ABA, as shown in Figure 1, or ABC (rhombohedral) stacking [1, 12]. Bernal stacking (ABA) is a common hexagonal structure which has been found in graphite. However, some parts of graphite can also have a rhombohedral structure (the ABC stacking) [6, 13]. The band structure of ABA-stacked TGNs can be assumed as a hybrid of monolayer and bilayer graphene band structures. The perpendicular external applied electric or magnetic fields are expected to induce band crossing variation in Bernal-stacked TGNs [14–16]. Figure 1 indicates that the graphene plane being a two-dimensional (2D) honeycomb lattice is the origin of the stacking order in multilayer graphene with A and B and two non-equivalent sublattices.

As shown in Figure 1, a TGN with ABA stacking has been modeled in the form of three honeycomb lattices with pairs of equivalent sites as {A_{1},B_{1}}, {A_{2},B_{2}}, and {A_{3},B_{3}} which are located in the top, center, and bottom layers, respectively [11]. An effective-mass model utilizing the Slonczewski-Weiss-McClure parameterization [17] has been adopted, where every parameter can be compared with a relevant parameter in the tight-binding model. The stacking order is related to the electronic low-energy structure of 3D graphite-based materials [18, 19]. Interlayer coupling has been found to also affect the device performance, which can be decreased as a result of mismatching the A-B stacking of the graphene layers or rising the interlayer distance. A weaker interlayer coupling may lead to reduced energy spacing between the subbands and increased availability of more subbands for transfer in the low-energy array. Graphene nanoribbon (GNR) has been incorporated in different nanoscale devices such as interconnects, electromechanical switches, Schottky diodes, tunnel transistors, and field-effect transistors (FETs) [20–24]. The characteristics of the electron and hole energy spectra in graphene create unique features of graphene-based Schottky transistors. Recently, the fabrication and experimental studies as well as a hypothetical model of G-Schottky transistors have been presented [25]. The studies have focused towards the properties of TGN, and a tunable three-layer graphene single-electron transistor was experimentally realized [6, 26].

Due to the fact that the GNR channel is sandwiched or wrapped through by the gate, the field lines from the source and drain contacts were seen to be properly screened by the gate electrodes, and therefore, the source and drain contact geometry has a lower impact. The operation of TGN SB FET is followed by the creation of the lateral semimetal-semiconductor-semimetal junction under the controlling top gate and relevant energy barrier.

## Methods

### TGN SB FET model

*υ*

_{ F }|

*k*| «

*V*«

*t*

_{⊥}gives the electronic band structure of TGN as [35, 39]

*k*is the wave vector in the

*x*direction, $\alpha =\frac{{v}_{\mathrm{f}}.V}{{t}_{\perp}\sqrt{2}},\beta =\frac{{v}_{\mathrm{f}}3}{{t}_{\perp}\sqrt{2}V}$,

*t*

_{⊥}is the hopping energy,

*ν*

_{f}is the Fermi velocity, and

*V*is the applied voltage. The response of ABA-stacked TGN to an external electric field is different from that of mono- or bilayer graphene. Rather than opening a gap in bilayer graphene, this tuned the magnitude of overlap in TGN. Based on the energy dispersion of biased TGN, wave vector relation with the energy (

*E*-

*k*relation) shows overlap between the conduction and valence band structures, which can be controlled by a perpendicular external electric field [6, 39]. The band overlap increases with increasing external electric field which is independent of the electric field polarity. Moreover, it is shown that the effective mass remains constant when the external electric field is increased [3, 33]. As an essential parameter of TGNs, density of states (DOS) reveals the availability of energy states, which is defined as in [40, 41]. To obtain this amount, derivation of energy over the wave vector is required. Since DOS shows the number of available states at each energy level which can be occupied, therefore, DOS, as a function of wave vector, can be modeled as [39]

*E*is the energy band structure and

*A*,

*B*,

*C*,

*D*, and

*F*are defined as

*A*= −6.2832

*α*,

*B*= 14.3849

*α*

^{2}

*β*, $C=\frac{2.7444}{\beta}$,

*D*= −9

*β*

^{2}, and $\phantom{\rule{0.25em}{0ex}}F=\frac{-0.1690{\alpha}^{3}}{\beta}$. As shown in Figure 4, the DOS for ABA-stacked TGN at room temperature is plotted. As illustrated, the low-DOS spectrum exposes two prominent peaks around the Fermi energy [39].

*M*and

*N*are defined as $M=\frac{{E}_{\mathrm{c}}}{{k}_{\mathrm{B}}T}$ and $\phantom{\rule{0.25em}{0ex}}N=\frac{F}{{\left({k}_{\mathrm{B}}T\right)}^{2}}$. Based on this model, ABA-stacked TGN carrier concentration is a function of normalized Fermi energy (

*η*). The conductance of graphene at the Dirac point indicates minimum conductance at a charge neutrality point which depends on temperature. For a 1D TGN FET, the GNR channel is assumed to be ballistic. The current from source to drain can be given by the Boltzmann transport equation in which the Landauer formula has been adopted [44, 45]. The number of modes in corporation with the Landauer formula indicates conductance of TGN that can be written as [32]

*k*) can be derived by using Cardano's solution for cubic equations [46]. Equation 4 can be assumed in the form

*G = N*

_{1}

*G*

_{1}

*+ N*

_{2}

*G*

_{2}, where

*N*

_{1}= 2

*αq*

^{2}/

*lh*and

*N*

_{2}= −6

*βq*

^{2}/

*lh*. Since

*G*

_{1}is an odd function, its value is equivalent to zero. Therefore,

*G*=

*N*

_{2}

*G*

_{2}[32], where

*x*= (

*E*− Δ)/

*k*

_{B}

*T*and

*η*= (

*E*

_{F}− Δ)/

*k*

_{B}

*T*. Thus, the general conductance model of TGN will be obtained [32] as

It can be seen that the conductivity of TGN increases by raising the magnitude of gate voltage. In the Schottky contact, electrons can be injected directly from the metal into the empty space in the semiconductor. When electrons flow from the valence band of the semiconductor into the metal, there would be a result similar to that for holes injected into the semiconductor. So, the establishment of an excess minority carrier hole in the vicinity is observed [28]. The current moves mainly from the drain to the source which consists of both drift and diffusion currents. The created 2D anticipated framework is expected to cause an explicit analytical current equation in the subthreshold system. Considering the weak inversion region, the diffusion current is mainly dominated and relative to the electron absorption at the virtual cathode [47]. A GNR FET is a voltage-controlled tunnel barrier device for both the Schottky and doped contacts.

The drain current through the barrier consists of thermal and tunneling components [48]. The effect of quantum tunneling and electrostatic short channel is not treated, which makes it difficult to study scaling behaviors and ultimate scaling limits of GNR SB FET where the tunneling effect cannot be ignored [20]. The tunneling current is the main component of the whole current which requires the use of the quantum transport. Close to the source within the band gap, carriers are injected into the channel from the source [49]. In fact, the tunneling current plays a very important role in a Schottky contact device.

The proposed model includes tunneling current through the SB at the contact interfaces, appropriately capturing the impact of arbitrary electrical and physical factors. The behavior of the proposed transistor over the threshold region is obtained by modulating the tunneling current through the SBs at the two ends of the channel [20]. The effect of charges close to the source for a SB FET is more severe because they have a significant effect on the SB and the tunneling possibility. When the charge impurity is situated at the center of the channel of a SB FET, the electrons are trapped by the positive charge and the source-drain current is decreased. If the charges are situated close to the drain, the electrons will collect near the drain. In this situation, low charge density near the source decreases the potential barrier at the beginning of the channel, which opens up the energy gap more for the flow of electrons from the source to the channel [50].

*J*

_{m→s}, whereas the electron current density

*J*

_{s→m}refers to the movement of electrons from the semiconductor into the metal. What determines the direction of electron flow depends on the subscripts of the current. In other words, the conventional current direction is opposite to the electron flow.

*J*

_{s→m}is related to the concentration of electrons with velocity in the x direction to subdue the barrier [28]:

*e*is the magnitude of the electronic charge and

*ν*

_{x}is the carrier velocity in the direction of transport:

*V*

_{A}is the applied bias voltage and

*V*

_{T}is the thermal voltage) [51]. The dependence of the drain current on the drain-source voltage is associated with the dependence of

*η*on this voltage given by

*V*

_{GT}=

*V*

_{GS}−

*V*

_{T}and

*V*(y) is the voltage of channel in the

*y*direction. By solving Equation 11, the normalized Fermi energy can be defined as

where *l* is the length of the channel.

## Results and discussion

*I*-

*V*) characteristic cannot be concealed by engineering the SB height when the gate insulator is thin. Lowering the gate insulator thickness and the contact size leads to thinner SBs and also greater on-current. Since the SB height is half of the band gap, the minimum currents exist at the gate voltage of

*V*

_{G,min}= 1/2

*V*

_{D}, at which the conduction band that bends at the source extreme of the channel is symmetric to the valence band and also bends at the drain end of the channel, while the electron current is the same as the hole current. The consequence of attaining the least leakage current is the same as TGN SB FET with middle-gap SBs [23]. Raising the drain voltage leads to an exponential increase of the minimal leakage current which shows the importance of proper designing of the power supply voltage to ensure small leakage current. As depicted in Figure 6, the proposed model points out strong gate-source voltage dependence of the current–voltage characteristic showing that the

*V*

_{GS}increment effect will influence the drain current. In other words, as

*V*

_{GS}increases, a greater value of

*I*

_{D}results. As the drain voltage rises, the voltage drop through the oxide close to the drain terminal reduces, and this shows that the induced inversion charge density close to the drain also decreases [28]. The slope of the

*I*

_{D}versus

*V*

_{DS}curve will reduce as a result of the decrease in the incremental conductance of the channel at the drain. This impact is indicated in the

*I*

_{D}-

*V*

_{DS}curve in Figure 6. If

*V*

_{DS}increases to the point that the potential drop across the oxide at the drain terminal is equal to

*V*

_{T}, the induced inversion charge density is zero at the drain terminal. At that point, the incremental conductance at the drain is

*nil*, meaning that the slope of the

*I*

_{D}-

*V*

_{DS}curve is zero. We can write

*V*

_{DS}(sat) is the drain-to-source voltage which is creating zero inversion charge density at the drain terminal. When

*V*

_{DS}is more than the

*V*

_{DS}(sat) value, the point in the channel where the inversion charge is zero moves closer to the source terminal [28]. In this case, electrons move into the channel at the source and pass through the channel towards the drain, and then at that point when the charge goes to zero, the electrons are infused into the space charge region where they are swept by the E-field to the drain contact. Compared to the original length

*L*, the change in channel length Δ

*L*is small, then the drain current will be regular for

*V*

_{DS}>

*V*

_{DS}(sat). The region of the

*I*

_{D}-

*V*

_{DS}characteristic is referred to as the saturation region. When

*V*

_{GS}is changed, the

*I*

_{D}-

*V*

_{DS}curve will also be changed. It was found that if

*V*

_{GS}increases, the initial slope of

*I*

_{D}-

*V*

_{DS}will be raised. We can also infer from Equation 14 that the value of

*V*

_{DS}(sat) is a function of

*V*

_{GS}. A family of curves is created for this n-channel enhancement-mode TGN SB FET, as shown in Figure 6.

*V*

_{GS}, the saturation current increases, showing the fact that a larger voltage drop occurs between the gate and the source contact. Also, there is a bigger energy value for carrier injection from the source contact channel [20]. The impact of power supply up-scaling decreases the SB length at the drain side, allowing it to be more transparent and resulting in more turn-on current to flow. Therefore, an acceptable performance comparable to the conventional behavior of a Schottky transistor is obtained. The scaling of the channel length improves gate electrostatic control, creating larger transconductance and smaller subthreshold swings. The effect of the channel length scaling on the

*I*-

*V*characteristic of TGN SB FET is investigated in Figure 7. It shows a similar trend when the gate-source voltage is changed. It can be seen that the drain current rises substantially as the length of the channel is increased from 5 to 50 nm.

To get a greater insight into the effect of increasing channel length on the increment of the drain current, two important factors, which are the transparency of SB and the extension of the energy window for carrier concentration, play a significant role [49, 50]. For the first parameter, as the SB height and tunneling current are affected significantly by the charges close to the source of SB FET, the channel length effect on the drain current through the SB contact is taken into account in our proposed model. Moreover, when the center of the channel of the SB FET is unoccupied with the charge impurities, the drain-source current increases because of the fact that free electrons are not affected by positive charges [49]. The effect of the latter parameter appears at the beginning of the channel where the barrier potential decreases as a result of low charge density near the source. This phenomenon leads to widening the energy window and ease of electron flow from the source to the channel [50]. Furthermore, due to the long mean free path of GNR [52–55], the scattering effect is not dominant; therefore, increasing the channel length will result in a larger drain current.

For a channel length of 5 nm, direct tunneling from the source to drain results in a larger leakage current, and the gate voltage may rarely adjust the current. The transistor is too permeable to have a considerable disparity among on-off states. For a channel length of 10 nm, the drain current has improved to about 1.3 mA. The rise in the drain current is found to be more significant for channel lengths higher than 20 nm. That is, by increasing the channel length, there is a dramatic rise in the initial slope of *I*_{D} versus *V*_{DS}. Also, based on the subthreshold slope model and the following simulated results, a faster device with opposite subthreshold slope or high on/off current ratio is expected. In other words, it can be concluded that there is a fast transient between on-off states. Increasing the channel length to 50 nm resulted in the drain current to increase by about 6.6 mA. The operation of the state-of-the-art short-channel TGN SB FET is found to be near the ballistic limit. Increasing further the channel length hardly changes neither the on-current or off-current nor the on/off current ratio. However, for a conventional *metal-oxide-semiconductor field-effect transistor (* MOSFET), raising the channel length may result in the channel resistance to proportionally increase. Therefore, in this case, down-scaling the channel length will result in significant loss of the on/off current ratio as compared to the SG device.

*I*-

*V*characteristics of other types of transistors [49, 50]. As depicted in Figure 8, the proposed model has a larger drain current than those transistors for some value of the drain-source voltages. The resultant characteristics of the presented model shown in Figure 8 are in close agreement with published results [49, 50]. In Figure 8, DG geometry is assumed for the simulations instead of the SG geometry type.

In order to have a deep quantitative understanding of experiments involving GNR FETs, the proposed model is intended to aid in the design of such devices. The SiO_{2} gate insulator is 1.5 nm thick with a relative dielectric constant *K* = 3.9 [50] (Figure 8a). Furthermore, the gate-to-channel capacitance *C*_{g} is a serial arrangement of insulator capacitance *C*_{ins} and quantum capacitance *C*_{q} (equivalent to the semiconductor capacitance in conventional MOSFETs). Figure 8b shows a comparative study of the presented model and the typical *I*-*V* characteristic of a TGN MOSFET with an ionic liquid gate. The availability of the ionic liquid gating [49] that can be modeled as a wrap-around gate of a corresponding oxide thickness of 1 nm and a dielectric constant *ε*_{r} = 80 results in *C*_{ins} >> *C*_{q}, and MOSFETs function close to the quantum capacitance limit, i.e., *C*_{g} ≈ *C*_{q}[49]. As depicted in Figure 8c,d, the comparison study of the proposed model with a TGN MOSFET with a 3-nm ZrO_{2} wrap-around gate for two different values of *V*_{GS} is notable. A 3-nm ZrO_{2} (*ε*_{r} = 25) wrap-around gate has *C*_{ins} comparable to *C*_{q} for solid-state high-*κ* gating, and this is an intermediate regime among the MOSFET limit and *C*_{q} limit.

Recently, a performance comparison between the GNR SB FETs and the MOSFET-like-doped source-drain contacts has been carried out using self-consistent atomistic simulations [20, 21, 48–50, 56, 57]. The MOSFET demonstrates improved performance in terms of bigger on-current, larger on/off current ratio, larger cutoff frequency, smaller intrinsic delay, and better saturation behavior [21, 50]. Disorders such as edge roughness, lattice vacancies, and ionized impurities have an important effect on device performance and unpredictability. This is because the sensitivity to channel atomistic structure and electrostatic environment is strong [50]. However, the intrinsic switching speed of the GNR SB FET is several times faster than that of the Si MOSFETs. This could lead to promising high-speed electronics applications, where the large leakage of the GNR SB FET is of fewer concerns [20]. An efficient functionality of the transistor with a doped nanoribbon has been noticed in terms of on/off current ratio, intrinsic switching delay, and intrinsic cutoff frequency [48].

Based on the presented model, comparable with the other experimental and analytical models, the on-state current of the MOSFET-like GNR FET is 1 order of magnitude higher than that of the TGN SB FET. This is because the gate voltage ahead of the source-channel flat band condition modulates both the thermal and tunnel components in the on-state of MOSFET-like GNR FET, while it modulates the tunnel barrier only of the metal Schottky-contact TGN FET that limits the on-state current. Furthermore, TGN SB FET device performance can be affected by interlayer coupling, which can be decreased by raising the interlayer distance or mismatching the A-B stacking of the graphene layers.

It is also noteworthy that MOSFETs operate in the region of subthreshold (weak inversion) as the magnitude of *V*_{GS} is smaller than that of the threshold voltage. In the weak inversion mode, the subthreshold leakage current is principally as a result of carriers' diffusion [58, 59]. The off-state current of the transistor (*I*_{OFF}) is the drain current when *V*_{GS} = 0. The off-state current is affected by some parameters such as channel length, channel width, depletion width of the channel, gate oxide thickness, threshold voltage, channel-source doping profiles, drain-source junction depths, supply voltage, and junction temperature [59].

*S*(mV/decade), is evaluated by selecting two points in the subthreshold region of an

*I*

_{D}-

*V*

_{GS}graph as the subthreshold leakage current is adjusted by a factor of 10. It has been noted that self-consistent electrostatics and the gate bias-dependent electronic structure have an essential role in determining the intrinsic limits of the subthreshold slope in a TGN SB FET, which stays well over the Boltzmann limit of the ideal value of 60 mV/decade or less than 85mV/decade [58, 63].The subthreshold slope, as one of the key issues of deep-submicrometer devices, is defined as [59]

*V*

_{t}is the threshold voltage,

*V*

_{off}is the off voltage of the device,

*I*

_{vt}is the drain current at threshold, and

*I*

_{off}is the current at which the device is off. In other words, the subthreshold slope delineates the inverse slope of the log (

*I*

_{D}) versus

*V*

_{GS}plotted graph as illustrated in Figure 10.

*l*= 100 nm) is obtained as shown in Table 1.

**Subthreshold slope of TGN SB FET at different values of**
V
_{
DS
}

V | 1 | 1.1 | 1.2 | 1.3 | 1.4 | 1.5 |
---|---|---|---|---|---|---|

Subthreshold slope (mV/decade) | 59.5238 | 54.1419 | 49.6032 | 45.8085 | 42.5134 | 39.2542 |

Based on data from [64], for the effective channel lengths down to 100 nm, the calculated and simulated subthreshold slope values are near to the classical value of approximately 60 mV/decade. The subthreshold slope can be enhanced by decreasing the value of the buried oxide capacitance *C*_{BOX} or by increasing the value of the gate oxide capacitance *C*_{GOX}[64]. Based on the simulated results, it can be concluded that when the channel material is replaced by TGN, the subthreshold swing improves further.

The comparison study between the presented model with data from [62, 64] showed that due to the quantum confinement effect [39, 43], the value of the subthreshold slope in the case of TGN SB FET is less than those of DG metal oxide semiconductor and vertical silicon-on-nothing FETs [62, 64] for some values of drain-source voltage. A nanoelectronic device characterized by a steep subthreshold slope displays a faster transient between on-off states. A small value of *S* denotes a small change in the input bias which can modulate the output current and thus leads to less power consumption. In other words, a transistor can be used as a high-speed switch when the value of *S* is small. As a result, the proposed model can be applied as a useful tool to optimize the TGN SB FET-based device performance. It showed that the shortening of the top gate may lead to a considerable modification of the TGN SB FET current–voltage properties. In fact, it also paves a path for future design of the TGN SB devices.

## Conclusions

TGN with different stacking arrangements is used as metal and semiconductor contacts in a Schottky transistor junction. The ABA-stacked TGN in the presence of an external electric field is also considered. Based on this configuration, an analytical model of junction current–voltage characteristic of TGN SB FET is presented. The dependence of the drain current versus the drain-source voltage of TGN SB FET as well as the back-gate and top-gate voltages for different values of gate-source voltage and geometric parameters such as channel length are calculated. In particular, we conclude that by increasing the applied voltage and also channel length, the drain current increases, which showed better performance in comparison with the typical behavior of other kinds of transistors. Finally, a comparative study of the presented model with MOSFET with a SiO_{2} gate insulator, a TGN MOSFET with an ionic liquid gate, and a TGN MOSFET with a ZrO_{2} wrap-around gate was presented. The proposed model is also characterized by a steep subthreshold slope, which clearly gives an illustration of the fact that the TGN SB FET shows a better performance in terms of transient between off-on states. The obtained results showed that due to the superior electrical properties of TGN such as high mobility, quantum transport, 1D behaviors, and easy fabrication, the suggested model can give better performance as a high-speed switch with a low value of subthreshold slope.

## Declarations

### Acknowledgements

The authors would like to acknowledge the financial support from a Research University grant of the Ministry of Higher Education (MOHE), Malaysia, under Projects Q.J130000.7123.02H24, PY/2012/00168, and Q.J130000.7123.02H04. Also, thanks to the Research Management Center (RMC) of Universiti Teknologi Malaysia (UTM) for providing excellent research environment in which to complete this work.

## Authors’ Affiliations

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