Performance improvement of phase-change memory cell using AlSb3Te and atomic layer deposition TiO2 buffer layer
© Song et al.; licensee Springer. 2013
Received: 16 November 2012
Accepted: 30 December 2012
Published: 15 February 2013
A phase change memory (PCM) cell with atomic layer deposition titanium dioxide bottom heating layer is investigated. The crystalline titanium dioxide heating layer promotes the temperature rise in the AlSb3Te layer which causes the reduction in the reset voltage compared to a conventional phase change memory cell. The improvement in thermal efficiency of the PCM cell mainly originates from the low thermal conductivity of the crystalline titanium dioxide material. Among the various thicknesses of the TiO2 buffer layer, 4 nm was the most appropriate thickness that maximized the improvement with negligible sacrifice of the other device performances, such as the reset/set resistance ratio, voltage window, and endurance.
Keywordsphase change memory atomic layer deposition TiO2 buffer layer reset voltage AlSb3Te
Phase change memory (PCM) has been regarded as the one of the most promising nonvolatile memories for the next generation because of the advantages of high speed, low power, good endurance, high scalability, and fabrication compatibility with complementary metal-oxide-semiconductor (CMOS) process [1–4]. PCM uses the reversible phase change between the crystalline and amorphous states of chalcogenide materials brought about by Joule heating. Ge2Sb2Te5 (GST) is the most widely used due to its relatively good trade-off between thermal stability and crystallization speed. However, with low crystallization temperature (around 140°C), GST is susceptible to the issue of thermal cross-talk by the proximity effect . The high reset current (mA) results in high power consumption for GST-based PCM . The switching speed, which is limited by its nucleation-dominated crystallization mechanism, is insufficient to satisfy the requirement of dynamic random access memory (around 10 ns) is also not satisfactory . These issues stimulate us to explore novel material system in order to improve the storing media characteristics. Compared with GST, Sb-rich Sb-Te materials have many advantages such as low melting point and fast crystallization . However, it is difficult to guarantee a satisfactory data-retention time at 80°C due to its relatively low crystallization temperature . Recently, the Al-Sb-Te (AST) ternary system has been proposed for application in electric memory [10, 11]. Compared with GST, Al-Sb-Te exhibits a high crystallization temperature, good data retention, and high switching speed.
It was reported that merely 0.2% to 1.4% of the total applied energy is effectively used for phase changing, and nearly 60% to 70% of the energy transfers back along the columnar tungsten (W) bottom electrode, having not participated in the heating process of the phase change material (for a T-shaped PCM cell) . Such a low thermal efficiency inevitably leads to a large operating bias/current during the phase change processes. Consequently, one of the effective solutions that has been tried to enhance the thermal efficiency is using an appropriate heating layer between the phase change material layer and the underlying W electrode, or replacing the W plug with some other suitable material. There are some qualified materials that have already been applied in reducing the programming current, such as TiON , Ta2O5, SiGe , TiO2[16, 17], SiTaN x , C60 , and WO3. All these materials have the common physical characteristics of high electrical resistivity and low thermal conductivity. Indeed, a heater material with a large electrical resistivity (>0.1 Ω cm) but low thermal conductivity is most favorable for heat generation and restriction in a PCM cell.
Titanium oxide (TiO2) is an n-type semiconductor and has very low thermal conductivity (approximately 0.7 to 1.7 W m-1 K-1 for 150- to 300-nm thick film) . Note that the thermal conductivity will be even less for a thinner TiO2 film. The electrical resistivity of a crystalline TiO2 film measured by the van der Pauw method in this study is about 1.2 Ω cm, which is close to the result reported by Xu et al. . In addition, TiO2 has a high melting point (approximately 2116 K) and will be thermally stable under high temperature (approximately 900 K) during the reset operation. Generally speaking, with the suitable electrical resistivity, thermal conductivity and thermal stability, a crystalline TiO2 layer should hopefully serve as the bottom heating layer in PCM cells to improve the thermal efficiency and, therefore, reduce the power requirement during phase transitions. In this study, the atomic layer deposition (ALD) TiO2 was used as a buffer layer which was expected to improve the thermal efficiency and reduce the reset voltage of PCM.
Results and discussion
Figure 4b and Figure 5b,d,e show the repeatable resistance switching between the set and reset states of the cells without and with TiO2 layer, respectively. For the device without TiO2, as shown in Figure 4b, the endurance capability keeps about 20,000 cycles before the presence of resistance disorder with a set stuck failure mechanism. For the device with 2 nm TiO2, as shown in Figure 5b, the reset resistance reduced gradually during the cycling. After 14,000 cycles, the reset resistance dropped rapidly, leading to the endurance failure by losing the set and reset resistance window. For the device with 8 nm TiO2, as shown in Figure 5f, the endurance capability keeps about 2,700 cycles before the presence of resistance disorder with a reset stuck failure mechanism. Good endurance characteristics (>104 cycles) was found in the cell with 4-nm TiO2 buffer layer. The low resistance state maintained around 103 Ω magnitude, and the high resistance state kept on 105 Ω level, indicating a satisfactory data resolution capability for random access memory application. The difference cyclic operation behavior shown in Figure 4b and Figure 5b,d,e suggested the different performance degradation processes for the device with and without TiO2 layer, which is currently under investigation. Among the various thicknesses of the TiO2 buffer layer, 4 nm was the most appropriate thickness that maximized the improvement with negligible sacrifice of the other device performances, such as the reset/set resistance ratio, voltage window, and endurance.
This paper reports an efficient method for reducing the reset voltage and power of the conventional T-shaped PCRAM, which has the potential to replace the current nonvolatile memories. We inserted TiO2 layer between phase change memory and bottom electrode to increase the utilization of the Joule heat and reduce the heat dissipation. Due to the suitable electrical resistivity and the low thermal conductivity of TiO2 film, the overall set resistance of the PCM cell will not be greatly increased, while the remarkably increased overall thermal resistance helps to reduce the reset voltage.
SS is an associate professor at the State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences.
This work was supported by the National Key Basic Research Program of China (2010CB934300, 2011CB9328004, and 2011CBA00607), the National Integrate Circuit Research Program of China (2009ZX02023-003), the National Natural Science Foundation of China (61006087, 61076121, 61176122, and 61106001), the Science and Technology Council of Shanghai (11DZ2261000 and 1052nm07000), and the Chinese Academy of Sciences (20110490761).
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