Growth of low temperature silicon nano-structures for electronic and electrical energy generation applications
© Gabrielyan et al.; licensee Springer. 2013
Received: 8 October 2012
Accepted: 10 January 2013
Published: 15 February 2013
This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapour-liquid–solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapour deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used.
The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices.
KeywordsSilicon nano-wire Nano-tree Gallium PECVD Solar cell Schottky diode Bistable memory
Silicon nano-wires (SiNWs) have attracted the attention of many researchers due to their structural, optical, electrical and thermoelectric properties. They are expected to be important building blocks in the future nano-electronic and photonic devices including solar cells, field-effect transistors, memory devices and chemical and biomedical sensors. Owing to their compatibility with the Si-base technology, SiNWs can be used not only as the functional units of the devices but also as the interconnects [1–6].
Various methods have been reported for SiNW fabrication, including both bottom-up and top-down techniques. Bottom-up growth methods include laser ablation, evaporation, solution-based methods and chemical vapour deposition (CVD). The CVD growth usually takes place via vapour-liquid-solid (VLS) route . Many catalyst materials, mainly metals including Au, Al, Ni, Fe and Ag, have been used for the SiNW growth [1, 8]. Among these metals, Au as catalyst has been the most popular and most widely investigated due to its chemical inertness and low eutectic temperature of Au-Si system. However, Au introduces deep impurity levels in Si bandgap and degrades the charge carrier mobility . Therefore, alternative catalyst investigation is of crucial importance.
One of the important parameters when considering the nano-wire fabrication process is the growth temperature, as this can determine the variety of substrates that could be used, especially when there is a prefabricated layer of some temperature-dependent material. The nano-wire growth temperature is determined by the eutectic temperature of the catalyst-precursor alloy ; thus, the low-temperature growth will depend on the appropriate catalysts choice. Considering the characteristics of Ga, including the Ga/Si alloy low eutectic point of 29.774°C, wide temperature range for silicon solubility and its non-reactivity to form solid compound with silicon, Ga has been suggested as a good alternative to Au to grow SiNWs at low-temperatures. It is important to note that Ga does not act as catalyst for the decomposition of precursor gas as it does not assist the dissociation of SiH4 below its thermal decomposition point. Therefore, Ga acts only as a solvent, and the decomposition is achieved by plasma treatment (by the use of plasma-enhanced chemical vapour deposition (PECVD) system) .
In this study, Ga catalyst is used with an aim to grow SiNWs at a lowest temperature using PECVD technique. The growth temperature was varied between 100°C and 400°C. The grown nano-structures were characterised using scanning electron microscopy (SEM), Ultra Violet Visible spectroscopy (UV-Vis) and Raman spectroscopy.
Electronic memory devices play a vital role in our everyday life. In the last a few decades, major progress has been observed focusing on the miniaturisation of the memory size cell while increasing its density. However, materials and fabrication techniques are reaching their limits. Alternative materials and architecture of memories, as well as manufacturing processes, are considered. In order to achieve this, different types of memories such as polymer, phase change and resistance have been reported in the literature [11–13]. Two-terminal non-volatile is one of the most promising memory types for fulfilling the aim of combining low cost, high density and small size devices . Therefore in this study, we present a two-terminal non-volatile memory based on SiNWs. The suitability and potential use of SiNWs for storage medium are investigated. The electrical behaviour of these devices was examined mainly in terms of current–voltage (I V) characteristics and data retention time (current-time) measurements.
Schottky diodes made of bulk materials do not dissipate heat quickly; hence, performance and lifespan of the device are reduced. Recently, one-dimensional (1D) nano-structures and their incorporation into Schottky diodes have been studied extensively. Due to their high surface-to-volume ratio and space between the nano-wires, diodes made of 1D nano-structure arrays can dissipate heat faster due to individual input from each wire. Therefore, integration of these nano-materials into the device will enhance its performance and lifespan . The as-grown SiNWs fabricated in this study were also used in a Schottky diode, and the electrical behaviour of the device is analysed.
Solar cells fabricated with nano-wires have shown several advantages when compared to wafer-based solar cells; some of them include trapping of light, less reflection and enhanced bandgap tuning. Although these advantages do not compete to attain efficiency more than efficiencies reported until today, they help in obtaining same efficiency or less by reducing the quantity and quality of the material. Nano-wires deposited by our growth method can have a number of benefits due to their possible fabrication directly on cheaper substrates including steel, bricks, aluminium foil and conductive glass, thus reducing the price of the solar cells based on these structures. In this study, SiNW-based Schottky solar cells were fabricated and their performance tested.
Silicon nano-wires were synthesised in a two-step growth process via VLS mechanism. At first, the gallium layer of various thicknesses was deposited onto soda-lime glass and Si/SiO2 substrates via thermal evaporation. SiO2 layer of 1 nm thickness was used as a barrier to prevent possible diffusion of Ga into Si. The thickness of the Ga layer was varied between 7.5 and 100 nm.
The samples were then loaded into an RF-PECVD reactor with radio frequency of 13.56 MHz and left for 4 h. Hydrogen gas was introduced into the chamber, while the substrate, coated with Ga layer, is being heated up to the growth temperature. Prior to introduction of the precursor gas, hydrogen plasma was created for 5 min in order to remove possible contamination and gallium oxide layer from the substrate. Silane (SiH4) was used as Si source. Gas flow rates, RF power, chamber pressure and deposition duration were process variables that have been investigated in detail and will be reported elsewhere.
Fabrication of bistable memory device
For the fabrication of a bistable memory device, glass substrate was used. Al contacts were deposited by thermal evaporation. Two silicon nitride (Si3N4) dielectric layers of 20 nm each were deposited in a PECVD system, sandwiching SiNWs between the bottom and top electrodes. SiNWs were grown for 30 min from 100-nm Ga catalyst layer at 400°C. After the Si3N4/SiNW/Si3N4/Al/glass structure was fabricated, the second layer of Al contacts was evaporated to finalise the device. The device characteristics were tested by I-V and data retention time measurements.
Fabrication of Schottky diode
SiNW-based Schottky diodes were fabricated by growing the SiNWs directly on glass substrate from 50 nm Ga at 400°C for 20 min with subsequent evaporation of both Al contacts on top of the nano-wires. The device characteristics were tested via I-V measurements.
Fabrication of solar cells
During solar cell fabrication, a glass substrate covered with transparent conductive oxide (TCO) layer (the details of the layer will be reported elsewhere) was utilised. SiNWs were grown on top of this layer from 50 nm Ga at 400°C for 40 min. Nano-wires for the solar cell were grown using additional phosphine in the reaction chamber for n-type doping of the nano-wires. After the nano-wire growth Al dots were evaporated for top contact.
Results and discussion
Low-temperature growth of silicon nano-wires
As mentioned in the ‘Methods’ section, SiNWs were grown from various thicknesses of Ga catalyst layer at various temperatures. An interesting connection between the thickness of Ga and growth temperature was observed. As it will be demonstrated in this study, the thickness of the catalyst layer is crucial when choosing the growth temperature.
This structure was only observed for thick gallium layers at only high temperatures. A possible explanation for this is that thick layers form large Ga particles (400 nm in diameter in average for 100-nm thick Ga layer) sitting at the top of the wires which stay in a molten form at high temperatures. Therefore, the molten form of Ga slides down, covering the surface of the wire creating smaller catalyst sites for growth of thinner nano-wires from the original nano-wire surface.
One of the possible explanations for the abovementioned dependence of the catalyst layer/growth temperature can be the following: (a) thinner layers at high temperatures get etched away by hydrogen plasma introduced for surface pre-treatment, therefore resulting in the absence of nano-wires for these samples, (b) thicker layers create particles of larger size which at low temperatures do not reach the Si solubility level sufficient to absorb enough Si to result in supersaturation and consequent precipitation of SiNWs, whereas the smaller particles require less Si for supersaturation, therefore result in nano-wire growth.
Overall, it can be concluded that in order to grow thin diameter nano-wires using thin catalyst layers (under 10 nm), lower growth temperatures should be used, whereas thick nano-wire and tree-like nano-structure growth require thick catalyst layer and high growth temperature.
Bistable memory device characteristics
After the initial charge loss, the two conductivity states were remained distinctive and stable as shown in Figure 7. These two states indicate that the device behaves as a non-volatile bistable memory.
Schottky diode characteristics
Solar cell characteristics
The curve in the bottom right quadrant is flat, which indicates high sheet and low shunt resistances. Shunt resistance is generally caused by leakage current which arises from pinholes and recombination traps in the active layer . It is reported that the leakage can also occur due to the shunting of surface leakage along with junction leakage . It has been reported that silicon structures grown by PECVD process usually contain bonding defects, interstitial atomic and molecular hydrogen, some voids which actually affect the activity of photo-generation of carriers .
The lowest temperature (150°C) for the growth of SiNWs via VLS mechanism is reported for the first time in literature. The growth was performed in the PECVD reactor using Ga catalyst layer. It was observed that the thickness of the Ga layer directly influences the choice of the growth temperature to be used for the nano-wire/nano-tree fabrication. The influence can be explained in two points: (a) high temperatures result in nano-tree growth from thicker layers (100 nm) of Ga, whereas thin Ga layers result in the absence of wires, (b) only thin catalyst layers (7.5 nm) initiate the growth of nano-wire arrays at low temperatures, whereas the only nano-wire growth observed from thicker layers was from between the larger particles from possible small Ga sites available.
A hysteresis of 0.96 nA was observed by the I-V characteristics of the bistable memory confirming the presence of charge trap carriers in the SiNWs. Furthermore, we detected the formation of two distinct conductivity states: a high (0) and a low (1), verifying the bistable behaviour of our memory. Schottky diode showed good rectifying behaviour with ideality factor of 17.68 and very low saturation current of 91.82 pA. Successful demonstration of silicon nano-structures to be used for Schottky diodes is shown in this paper. Though efficiency is low, silicon nano-structures play important role in light absorption which can be used as active layer for solar cells, demonstrated in this paper. Additionally, good stability of Voc over time is also observed in solar cells. The SiNW-based bistable memory device, Schottky diode and solar cell showed promising characteristics that could be optimised further for future applications in high performance electronic and electrical energy generation devices.
NG received her BS and MSc degrees in Physics from Yerevan State University, Armenia in 2006 and 2008, correspondingly. Currently, she is a Ph.D. student at Emerging Technologies Research Centre (EMTERC), De Montfort University, investigating fabrication of nanomaterials for biosensor application. KS received her BS degree in physics at Patras University, Greece in 2010 and her MSc degree in 2011 in Microelectronics and Nanotechnology at EMTERC, De Montfort University. Currently, she is a Ph.D. student at EMETRC, De Montfort University looking into fabrication of flash memory devices on plastic. KNM received his BS degree in Electronics and Communication from Visvesvaraya Technological University, India in 2010, and his MSc degree in 2012 in Microelectronics and Nanotechnology at EMTERC, De Montfort University. Currently, he is a Ph.D. student at EMTERC, De Montfort University working on nanomaterials for photovoltaic applications. SP received his MS from the Indian Institute of Science, Bangalore, India and his Ph.D. from De Montfort University. Currently, he is the head of EMTERC, De Montfort University. He has previously worked in Cambridge University, Durham University, and Rutgers University.
The authors would like to thank Mr. Matthew David Rosser, faculty of Health and Life Sciences, De Montfort University, Leicester, UK for his assistance with SEM imaging. The Authors are also thankful to De Montfort University for the postgraduate scholarships.
- Alvarez , et al.: Nanoscale Res Lett. 2011, 6: 110. 10.1186/1556-276X-6-110View Article
- Akhtar S, Usami K, Tsuchiya Y, Mizuta H, Oda S: Vapor–liquid–solid growth of small and uniform-diameter silicon nanowires at low temperature from Si2H6. Appl Phys Express 2008, 1(1):014003. 10.1143/APEX.1.014003View Article
- Chen X, Xing Y, Xu J, Xiang J, Yu D: Rational growth of highly oriented amorphous silicon nanowire films. Chem Phys Lett 2003, 374(5–6):626–630.View Article
- Cui Y, Lauhon LJ, Gudiksen MS, Wang J, Lieber CM: Diameter-controlled synthesis of single-crystal silicon nanowires. Appl Phys Lett 2001, 78(15):2214–2216. 10.1063/1.1363692View Article
- Peng KQ, Lee ST: Silicon nanowires for photovoltaic solar energy conversion. Adv Mater 2011, 23(2):198–215. 10.1002/adma.201002410View Article
- Shao M, Ma DDD, Lee ST: Silicon nanowires—synthesis, properties, and applications. Eur J Inorg Chem 2010, 27: 4264–4278.View Article
- Hofmann S, Ducati C, Neill RJ, Piscanec S, Ferrari AC, Geng J, Dunin-Borkowski RE, Robertson J: Gold catalyzed growth of silicon nanowires by plasma enhanced chemical vapor deposition. J Appl Phys 2003, 94(9):6005–6012. 10.1063/1.1614432View Article
- Hetzel M, Lugstein A, Zeiner C, Wójcik T, Pongratz P, Bertagnolli E: Ultra-fast vapour-liquid–solid synthesis of Si nanowires using ion-beam implanted gallium as catalyst. Nanotechnology 2011, 22: 395601. 10.1088/0957-4484/22/39/395601View Article
- Pan ZW, Dai ZR, Ma C, Wang ZL: Molten gallium as a catalyst for the large-scale growth of highly aligned silica nanowires. J Am Chem Soc 2002, 124(8):1817–1822. 10.1021/ja017284nView Article
- Gewalt A, Kalkofen B, Lisker M, Burte EP: Epitaxial growth of Si nanowires by a modified VLS method using molten Ga as growth assistant. MRS Proceedings 2009. 10.1557/PROC-1144-LL03-11
- He L, Liao ZM, Wu HC, Tian XX, Xu DS, Cross GLW, Duesberg GS, Shvets IV, Yu DP: Memory and threshold resistance switching in Ni/NiO core-shell nanowires. Nano Lett 2011, 11(11):4601–4606. 10.1021/nl202017kView Article
- Salaoru I, Paul S: Small organic molecules for electrically re-writable non-volatile polymer memory devices. Mater Res Soc Symp Proc 2010, 1250: 159–164.View Article
- Wang J, Dong X, Sun G, Niu D, Xie Y: Energy-efficient multi-level cell phase-change memory system with data encoding. In IEEE 29th International Conference on Computer Design (ICCD): November 9–12 2011; Amherst, MA. New York: IEEE; 2011:175–182.View Article
- Paul S: Realization of nonvolatile memory devices using small organic molecules and polymer. IEEE T Nanotechnol 2007, 6(2):191–195.View Article
- Das SN, Kar JP, Myoung J: Junction properties and applications of ZnO single nanowire based Schottky diode. In Nanowires—Fundamental Research. Edited by: Hashim AA. New York: InTech; 2011:161–182.
- Michaelson HG: Relation between an atomic electronegativity scale and the work function. IBM J Res Dev 1978, 22(1):72–80.View Article
- Kim J, Yun JH, Han CS, Cho YJ, Park J, Park YC: Multiple silicon nanowires-embedded Schottky solar cell. Appl Phys Lett 2009, 95: 143112. 10.1063/1.3245310View Article
- Fan Z, Ho JC, Jacobson ZA, Yerushalmi R, Alley RL, Razavi H, Javey A: Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing. Nano Lett 2008, 8(1):20–25. 10.1021/nl071626rView Article
- Landman U, Barnett RN, Scherbakov AG, Avouris P: Metal–semiconductor nanocontacts: silicon nanowires. Phys Rev Lett 2000, 85(9):1958–1961. 10.1103/PhysRevLett.85.1958View Article
- Bülbül MM, Bengi S, Dokme I, Altındal S, Tunc T: Temperature dependent capacitance and conductance-voltage characteristics of Au/polyvinyl alcohol (Co,Zn)/n-Si Schottky diodes. J Appl Phys 2010, 108(3):034517–034517–6. 10.1063/1.3462427View Article
- Ahmad Z, Sayyad MH: Extraction of electronic parameters of Schottky diode based on an organic semiconductor methyl-red. Physica E 2009, 41(4):631–634. 10.1016/j.physe.2008.08.068View Article
- Choi P, Kim H, Baek D, Choi B: A study on the electrical characteristic analysis of c-Si solar cell diodes. J Sem Tech Sci 2012, 12(1):58–65.
- Das SN, Pal AK: Properties of a nanocrystalline GaN p-n homojunction prepared by a high pressure sputtering technique. Semicond Sci Tech 2006, 21(12):1557–1562. 10.1088/0268-1242/21/12/010View Article
- Yu LS, Jia L, Qiao D, Lau SS, Li J, Lin JY, Jiang HX: The origins of leaky characteristics of Schottky diodes on p-GaN. IEEE T Electron Dev 2003, 50(2):292–296. 10.1109/TED.2002.808558View Article
- Schmidt V, Wittemann JV, Gösele U: Growth, thermodynamics, and electrical properties of silicon nanowires. Chem Rev 2010, 110(1):361–388. 10.1021/cr900141gView Article
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