Design and Analysis of Nanotube-Based Memory Cells
© to the authors 2008
Received: 3 June 2008
Accepted: 25 August 2008
Published: 9 September 2008
In this paper, we proposed a nanoelectromechanical design as memory cells. A simple design contains a double-walled nanotube-based oscillator. Atomistic materials are deposed on the outer nanotube as electrodes. Once the WRITE voltages are applied on electrodes, the induced electromagnetic force can overcome the interlayer friction between the inner and outer tubes so that the oscillator can provide stable oscillations. The READ voltages are employed to indicate logic 0/1 states based on the position of the inner tube. A new continuum modeling is developed in this paper to analyze large models of the proposed nanoelectromechanical design. Our simulations demonstrate the mechanisms of the proposed design as both static and dynamic random memory cells.
Due to their unique mechanical and electronic properties [1, 2], carbon nanotubes hold promise in designing novel nanoscale devices, such as scanning probe tips, field emission sources, molecular wires, and diodes. For example, Bachtold et al.  designed logic circuits with field-effect transistors using individual carbon nanotubes (CNT). Kinaret et al.  investigated the operational characteristics of a nanorelay in which a conducting CNT was placed on a terrace in a silicon substrate. Other proposed CNT-based devices include nanotube resonant oscillators , nano cantilevers , nanotube motors , and others. One of the exciting designs, proposed by Rueckes et al. , was nanotube-based non-volatile random access memory. In this design, each device element was based on a suspended, crossed nanotube geometry that leads to bistable, electrostatically switchable on/off states. Due to small size and low interlayer friction , double-walled nanotubes (DWNT) have been utilized as co-axial oscillators [10–12], which can have oscillation frequencies up to 72 GHz . Based on our previous investigations , we propose a conceptual design of nanotube-based memory cells in this paper and study the mechanisms of this device as static random access memory (SRAM) and dynamic random access memory (DRAM).
Molecular dynamics simulations  have shown that nanotube-based co-axial oscillators could cease at finite temperatures due to the interlayer friction between the inner and outer tubes. A higher temperature results in faster energy dissipation because of the larger interlayer friction. Consequently, stable oscillations could not be observed. To overcome the above issue, we propose a nanoelectromechanical (NEMS) design containing a nanotube-based co-axial oscillator to provide stable oscillation so that this design can be employed as memory cells. We also develop a continuum model in this paper to analyze the proposed NEMS memory cell design.
Design of Memory Cells
Atomic materials for the conducting electrodes 1 and 2 are deposited on the top of the outer nanotube. The electrode composition would be gold as well. Evaporation is certainly one mechanism for deposition of the electrode. It may also be possible to deposit the electrode by molecular beam epitaxy techniques. Using such techniques, the gold atoms will tend to bond with the carbon atoms at the outside surface of the nanotube, preventing their deposition on the inside of the nanotube.
In this configuration, the inner tube sits in a double-bottom electromagnetic potential well. The depth of the potential well under electrode 1 is proportional to the voltage applied to electrode 1; similarly, the depth of the potential well under electrode 2 is proportional to the voltage applied to electrode 2. The induced quasi-static electromagnetic forces exerted on the inner tube will overcome interlayer friction if the applied voltage is sufficiently large. This large applied voltage is referred to as the WRITE voltage. When a WRITE voltage is applied to the electrode, the inner tube may move due to the induced electromagnetic forces [14, 15]. Consequently, lateral motion of the inner tube will be induced as a result. Here, a capped outer tube is employed because the inner tube can easily escape from an open outer tube due to the induced electromagnetic forces. The capacitance of the NEMS gate can be read by a distinct READ process. A constant-current pulse is applied to one of the electrodes. If the inner CNT is present under that electrode, a relatively large capacitance will be observed, and the time required to charge the electrode will be longer. If the inner tube is not present under that electrode, a relatively small capacitance will be observed, as will a concomitant fast charging time for the electrode. As a result, the logic state of the NEMS gate can be determined. It should be noted that all READ voltages are sufficiently small so that the motion of the inner tube will not be influenced. Less than 5% of the WRITE voltage is recommended for the READ voltage. Whether the inner tube is underneath electrode 1 or electrode 2 will result in two different physical states determined by the READ voltage. These two different physical states can be interpreted as Boolean logic states. Therefore, the system can be used as a random access memory (RAM) cell. It should be noted that Kang and Hwang  proposed the similar NEMS design, called ‘Carbon nanotube shuttle’ memory device. However, our design is more specific, and we quantitatively illustrate the proposed design as SRAM and DRAM cells. In addition, the continuum model developed in this paper will help to study feasibility of large nanotube-based memory cells in practical applications.
Fabrication of arrays of nanotube structures such as we propose in this paper is a subject of much ongoing research. CNT geometric uniformity and the ability to position CNTs in a regular array suitable for addressing as a RAM memory cell are both issues that remain open. However, significant progress in this area is being made. In previous research , the researchers reported on a complete scheme for creating predefined networks of individual CNTs. Using a specialized CVD method to grow single-walled carbon nanotubes (SWNTs) on SiO2-capped Si pillars, coupled with spectroscopic techniques to map the specific tube geometries, the fabrication of regular arrays of CNTs suitable for use in integrated circuits has been demonstrated. Extension of these or other techniques for fabricating regular arrays of DWNTs will be required to implement our memory cell beyond the proof-of-concept stage.
where m I is the mass associated with particle I, u I is the displacement of particle I, and is the internal nodal force applied on particle I due to the deformation of the nanotube itself. The external nodal force, , contains two parts. One is due to the interlayer interaction between the inner tube and the outer tube, and the other is the induced electromagnetic force when applying voltage on the electrodes.
where A = 2.43 × 10−24 J nm and y 0 = 0.3834 nm. The interlayer equilibrium distance is 0.34 nm, which results in the minimum van der Waals energy. This distance matches the thickness of a graphene sheet, and it also satisfies the criterion proposed by Legoas et al.  for stable nanotube-based oscillators.
where ΩOand ΩIare the configurations of the outer and inner tubes, respectively. Then, the force applied on particle I can be derived as the first derivative of Φ with respect to the coordinates of particle I.
where v Iz is the z component of the velocity of particle I, and N is the number of atoms represented by particle I in the mesh-free particle model. Here,e z represents direction along the nanotube axis.
Results and Discussions
It is obvious that the frequency of the SRAM cell cannot exceed the natural frequency of its embedded nanotube-based oscillator. Since the nanotube-based oscillator is an underdamped system, the proposed design can be extended for application as a DRAM cell. In this configuration, the oscillator will continue to oscillate at its natural frequency. A WRITE voltage pulse is applied every several oscillation periods to stimulate oscillation of the oscillator. Consequently, a steady oscillation can be generated for logic states 0 and 1. As an example, the simulated DRAM cell included a 32-nm-long (17, 0) outer tube and an 18-nm-long (5, 5) inner tube. The open-ended outer tube instead of the capped one is employed. In this case, two 10-nm-long electrodes are attached on the top of the outer tube. Initially, the inner tube has a velocity of 400 m/s and is placed at the center of the outer tube. In this case, the natural oscillating frequency of the oscillator is 6.75 GHz. After every four cycles, a voltage of 48 V with a duration of 2 ps is applied at the electrode to increase the oscillatory amplitude. Consequently, the inner tube keeps a stable oscillation.
Nanotube-based oscillators can provide high oscillation frequencies. However, it is found that the oscillation could cease due to interlayer friction between the inner and outer tubes when the oscillator is at finite temperatures. Such a shortcoming prevents the nanotube-based oscillators from being utilized in nanodevices. We designed a new NEMS device via deposing atomic materials on the top of the outer tube as electrodes. Once a voltage is applied on the electrodes, the induced electrostatic force can overcome the interlayer friction. We developed a multiscale method to simulate the proposed design. Our simulations demonstrated that the designed device can be utilized as SRAM and DRAM. In this paper, the design and analysis procedure can be extended for other NEMS designs.
The authors acknowledge support from the National Science Foundation (Grant # 0630153).
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