# High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder

- K Navi
^{1}Email author, - M Rashtian
^{2}, - A Khatir
^{2}, - P Keshavarzian
^{2}and - O Hashemipour
^{1}

**Received: **31 January 2010

**Accepted: **1 March 2010

**Published: **18 March 2010

## Abstract

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.

## Keywords

## Introduction

Technology progress in all areas of life has resulted in a need for small devices with higher operating speeds, and this is why extensive researches in these fields have been completed. Finding a suitable alternative is necessary since when MOS transistors continue to scale deeper, several device non-idealities appear and cause significant intrinsic device hurdles such as leakage, power and quantum effect [1]. Molecular devices are becoming promising alternatives to the existing silicon technology. CNFETs are one of the molecular devices that avoid most fundamental silicon transistor restriction and have ballistic or near ballistic transport in their channel [2, 3].

_{on}/I

_{off}ratio becomes rather low [1]. Another type of CNFETs shown in Fig. 1b is doped in un-gated portions and has similar behavior to CMOS transistors; thus, this type is named MOSFET-Like CNFET. The features of MOSFET-Like CNFETs [4] are; unipolar characteristics dissimilar to Schottky-Barrier transistors, more scalability in comparison to SB-CNFET, reducing the OFF leakage current and having higher ON current in source-to channel junction because of absence of the Schottky Barrier. In this paper, we use the word CNFET instead of MOSFET-like device.

_{CNT}, CNFET threshold can be calculated by using (1), and formula (2) depict how CNT diameter can be calculated where N

_{1}and N

_{2}are chirality of CNT and α is the lattice constant equal to 2.49 Å

There are two methods by which new devices can be built using CNFETs; first one is by transporting existing logical functions directly to a new technology with replacing MOSFET with CNFET and the second one uses special properties of CNFETs to design entirely new circuit [4].

One of the important parts of the processor, which participates in many operations such as floating point computing and address generating [5], is Full Adders. Thus, increasing the performance of this part can improve total performance dramatically. There are standard implementations for Full Adder cells. Some of these implementations have used one logic style for the whole Full Adder and others that are hybrid Full Adders have used two or more logic style in a cell. Although they all have similar function, the way of designing intermediate nodes or the transistor count is varied. C-CMOS Full Adder cell uses one logic style [6] and is based on regular CMOS structure with conventional pull-up and pull-down transistors. The outputs are full swing, but with 28 transistors, it utilizes a large space in a chip. CPL is another Full Adder that uses one logic style. The outputs are full swing and make complementary outputs simultaneously, but the number of transistors used (transistor count) is 32 [7].

Design [11] uses four transistors and seven capacitors and has full swing outputs. In [12], two Full Adders are presented using CNFETs in their designs, one used four CNFETs and seven capacitors and the other utilized only two transistors but two resistors employed caused an increase to the power dissipation. In next section, we exploit CNFET characteristics in order to introduce a new Full Adder that uses eight Carbon Nanotube transistors with eight capacitors, and it has full swing outputs. In Sect. 3, we will compare it with contemporary Full Adder based on Carbon Nanotube transistor with delay, power consumption and power-delay product criterions.

## Proposed Full Adder

_{TH}for both NMOS and PMOS. This circuit can be used to implement NAND gate using high-V

_{TH}NMOS and low-V

_{TH}PMOS, and NOR gate using low-V

_{TH}NMOS and high-V

_{TH}PMOS [15]. Formula (1) and (2) in previous section illustrate how the appropriate CNFET threshold voltage can be calculated. As shown in Fig. 3, in this paper for designing NAND and NOR function, we calculate the output SUM by formula (5)

## Simulation Results

## Conclusion

In this paper, a novel high speed Majority-Not (Minority) function–based CNFET Full Adder is proposed. The main idea of this design is a new approach for implementing the SUM output. That is, SUM can be considered as Minority(A,B,C,2*Nand(A,B,C),2*Nor(A,B,C)). This adder has a simple design, because it only uses capacitors and inverter in its structure. Simulations are carried out using HSPICE simulator with CNFET model for proposed design. Inverters that are used in the outputs enhance the driving capability of the designs. Simulation results illustrate that we have achieved a significant improvement in terms of Delay and Power-Delay product.

## Declarations

### Acknowledgment

The authors would like to thank Dr. Belmond Yoberd for his literature contribution.

**Open Access**

This article is distributed under the terms of the Creative Commons Attribution Noncommercial License which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.

## Authors’ Affiliations

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