- NANO EXPRESS
- Open Access
High-Temperature Stable Operation of Nanoribbon Field-Effect Transistors
© The Author(s) 2010
Received: 29 June 2010
Accepted: 19 July 2010
Published: 3 August 2010
We experimentally demonstrated that nanoribbon field-effect transistors can be used for stable high-temperature applications. The on-current level of the nanoribbon FETs decreases at elevated temperatures due to the degradation of the electron mobility. We propose two methods of compensating for the variation of the current level with the temperature in the range of 25–150°C, involving the application of a suitable (1) positive or (2) negative substrate bias. These two methods were compared by two-dimensional numerical simulations. Although both approaches show constant on-state current saturation characteristics over the proposed temperature range, the latter shows an improvement in the off-state control of up to five orders of magnitude (−5.2 × 10−6).
The nanoribbon structure has recently been extensively investigated for many applications, such as ZnS nanoribbon lasers , graphene nanoribbon field-effect transistors (GNRFETs) , nanoribbon sensors in Si  and other materials . Nanoribbon structures offer a relatively easy system to access, control and process, due to their relatively larger scale compared to other nanostructures, such as nanowires (NWs) , nanodots (NDs)  and nanotubes (NTs) . Nanoribbons or thin silicon on insulators have many advantages, such as low leakage and a high on/off current ratio, ION/IOFF, which leads to low power consumption while the device is inactive . In addition, since their parasitic capacitance is effectively eliminated by the underlying insulating layer, nanoribbon- or thin silicon-based devices have advantages for RF applications . Such structures also have a lower threshold shift in response to temperature variations [10–13]. However, the reduction in mobility induced by the thermal scattering causes the operation points of the device to vary with the temperature. This temperature-dependent variation of the operation points makes the devices hard to operate properly.  For some high-temperature circuits, it is desirable that the individual devices have a specific operation point where the device characteristics show no variation with temperature. In this work, we demonstrate the feasibility of the constant operation of the fabricated devices in the temperature range from 25 to 150°C. The method employed to achieve the constant operation of the fabricated devices, which is similar to zero temperature coefficients (ZTC), is based on the use of a substrate bias (VSUB). By accumulating or depleting the carriers on the channel surface using the substrate bias (VSUB), we show that the device on/off characteristics show minimal variation with temperature.
We used a substrate bias (VSUB) to ensure the constant operation of the devices at elevated temperatures, and the measurements were compared with the two-dimensional simulation results obtained from structures identical to those of the fabricated devices . In order to evaluate the substrate and top bias-dependent channel carrier modulation as a function of temperature, we extracted the channel cross-section profiles containing the on- and off-current density distribution at different temperatures.
Results and Discussion
Figure 3a shows the drain characteristics of the fabricated (solid lines) and simulated (dashed lines) nanoribbon FETs as a function of temperature in the range between 25 and 150°C. Figure 3b, 3c, 3d and 3e show the channel cross-sections of the device, showing the conduction current density contours. Figure 3b and c show the conduction current density contours for the ‘on’ state at room temperature and T ~ 150°C, respectively. These two contour plots clearly indicate that the conduction current is reduced by the mobility degradation as the temperature increases. Figure 3d and 3e show the constant ‘off’ states at room temperature and T ~ 150°C, respectively.
Measured data shown as portion of leakage current levels (ILEAK/ION) in percentages (%) at different temperatures
Method 1 (%)
Method 2 (%)
5.2 × 10−6
2.5 × 10−6
2.8 × 10−5
3.2 × 10−3
9.8 × 10−3
In summary, we report the constant temperature operation of nanoribbon FETs in the temperature range of 25–150°C. In order to compensate for the variation in the current level with the temperature in the range from 25 to 150°C, we propose two methods. The physical mechanisms are; (1) to accumulate the lower part of semiconducting channel by applying a suitable negative substrate bias to enhance the total current level at elevated temperatures or (2) to deplete the lower part of the semiconducting channel by applying a positive substrate bias to reduce the total current level at lower temperatures. The leakage current level was drastically reduced by the negative substrate bias, as the carriers in the channel are effectively depleted, thus compensating for the fluctuating off-current level. Although both approaches show constant on-state current saturation characteristics over the proposed temperature range, the latter shows an improvement in the off-state control of up to five orders of magnitude (~5.2 × 10−6). These results were confirmed by two-dimensional numerical simulations, which show that the substrate bias causes the channel to be effectively depleted or accumulated.
This work was supported by National Research Foundation of Korea Grant funded by the Korean Government (2009-0066544 and 2010-0015360) and the Research Grant of Kwangwoon University in 2010.
This article is distributed under the terms of the Creative Commons Attribution Noncommercial License which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.
- Zapien JA, Jiang Y, Meng XM, Chen W, Au FCK, Lifshitz Y, Lee ST: Appl. Phys. Lett.. 2004, 84: 1189. COI number [1:CAS:528:DC%2BD2cXht1OgsLY%3D]; Bibcode number [2004ApPhL..84.1189Z] 10.1063/1.1647270View ArticleGoogle Scholar
- Luisiera M, Klimeck G: Appl. Phys. Lett.. 2009, 94: 223505. Bibcode number [2009ApPhL..94v3505L] 10.1063/1.3140505View ArticleGoogle Scholar
- Elfström N, Karlström AE, Linnros J: Nano Lett.. 2008, 8: 945–949. Bibcode number [2008NanoL...8..945E] 10.1021/nl080094rView ArticleGoogle Scholar
- Han XY, Gao YH, Zhang XH: Nano-Micro Lett.. 2009, 1: 4. COI number [1:CAS:528:DC%2BC3cXjvFemtrY%3D]View ArticleGoogle Scholar
- Koo S-M, Fujiwara A, Han J-P, Vogel EM: Nano Lett.. 2004, 4: 2197–2201. COI number [1:CAS:528:DC%2BD2cXnvFCqtLk%3D]; Bibcode number [2004NanoL...4.2197K] 10.1021/nl0486517View ArticleGoogle Scholar
- Hong AJ, Liu C-C, Wang Y, Kim J, Xiu F, Ji S, Zou J, Nealey PF, Wang KL: Nano Lett. ASAP. 2009.Google Scholar
- Gao X.P.A, Zheng G, Lieber Charles M: Nano Lett., Articles ASAP. 2009.Google Scholar
- Adan AO, Higashi K: IEEE Trans. Elec. Dev.. 2001, 48: 2050. Bibcode number [2001ITED...48.2050A] 10.1109/16.944195View ArticleGoogle Scholar
- Nii H, Yamada T, Inoh K, Shino T, Kawanaka S, Yoshimi M, Katsumata Y: IEEE Trans. Elec. Dev.. 2000, 47: 1536. COI number [1:CAS:528:DC%2BD3cXltl2lsbs%3D]; Bibcode number [2000ITED...47.1536N] 10.1109/16.848304View ArticleGoogle Scholar
- Kuroda T, Fujita T, Mita S, Nagamatsu T, Yoshioka S, Suzuki K, Sano F, Norishima M, Murota M, Kako M, Kinugawa M, Kakumu M, Sakurai T: IEEE J. Solid State Circuits. 1996, 31: 1770. 10.1109/JSSC.1996.542322View ArticleGoogle Scholar
- Colinge J-P: Silicon-on-Insulator Technology: Materials to VLSI. Kluwer, Norwell; 1997.View ArticleGoogle Scholar
- Flandre D, Terao A, Francis P, Gentinne B, Colinge JP: IEEE Electron Device Lett.. 1993, 14: 10–12. Bibcode number [1993IEDL...14...10F] 10.1109/55.215084View ArticleGoogle Scholar
- Flandre D: Mater. Sci. Eng.. 1995, B29: 7–12. COI number [1:CAS:528:DyaK2MXjt1Wiurg%3D] 10.1016/0921-5107(94)04018-YView ArticleGoogle Scholar
- Zolper JC: Solid-Stare Elecron.. 1998, 42: 2153–2156. COI number [1:CAS:528:DyaK1cXotFSjtr4%3D]; Bibcode number [1998SSEle..42.2153Z] 10.1016/S0038-1101(98)00210-XView ArticleGoogle Scholar
- 2007. ATLAS Manual by Silvaco International, 1-898Google Scholar
- Klaassen DBM: Solid-State Electron.. 1992, 35: 953. COI number [1:CAS:528:DyaK38XkvVWisb8%3D]; Bibcode number [1992SSEle..35..953K] 10.1016/0038-1101(92)90325-7View ArticleGoogle Scholar