- Nano Express
- Open Access
A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires
© Su et al; licensee Springer. 2012
- Received: 30 November 2011
- Accepted: 29 February 2012
- Published: 29 February 2012
In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.
- JL; NW
With the proliferation of portable electronic products, the demand of high density nonvolatile memories [NVMs] has boosted tremendously. Among various nonvolatile memory [NVM] architectures, the flash memory, based primarily on floating-gate [FG] devices, has dominated the mainstream NVM market for decades. FG devices, however, are inherently vulnerable to fatal data loss through a single defect in the tunnel oxide , and face stringent challenges in the course of device downscaling owing to the gate-coupling concern . In light of this, flash memory based on charge trapping [CT] devices, such as silicon-oxide-nitride-oxide-silicon [SONOS] multilayer structure  and its various derivatives [4, 5], has received renewed interest, and is extensively investigated recently. Being inherently immune to gate-coupling issue and more tolerant to the defects in the thin tunnel oxide, a SONOS memory device enables thinner gate stack height for stronger electrostatic control, and thus is more scalable. Concurrently, flash memory constructed on polycrystalline silicon thin-film transistors (poly-Si [TFTs]) has attracted enormous attention owing to the low-cost and low-temperature fabrication processes and its compatibility with system-on-panel [SOP] or system-on-chip integration [6, 7]. In addition, a thin-film transistor [TFT]-SONOS array is also attractive for three-dimensional [3-D] multilayer stack structure for the purpose of ultrahigh memory cells density without aggressive scaling of device dimensions . However, due to the grainy structure and defects associated with grain boundaries in the films, typical poly-Si TFT-based memory devices face some challenging issues, such as poor subthreshold swing [SS] and slow memory operation speed. Nevertheless, by employing nanowire [NW] channels with multiple-gated configuration in TFTs, the memory speed and subthreshold swing have been demonstrated to be significantly improved, thanks to better gate controllability and reduced defects in the small volume of NWs . Recently, we have developed a junctionless [JL] poly-Si NW transistor with enhanced drive current and reduced source/drain [S/D] series resistance using in situ heavily doped poly-Si . Such material features uniform doping concentration and is commonly used for gate electrode in the fabrication of field-effect transistors [FETs]. A JL transistor features the same doping polarity and concentration throughout the entire device, and thus alleviates the requirement of precise control of dopant distribution in the S/D regions . In this work, we further apply and investigate such scheme to SONOS flash memory device for the purpose of reducing the fabrication complexity and enhancing the programming efficiency by taking advantage of the higher carrier concentration in the JL NW channels.
Device fabrication and experiment
In summary, we have successfully demonstrated the feasibility of JL NW SONOS memory device by employing only one in situ-doped n+-poly-Si layer. In addition to the much simplified fabrication process, the fabricated device displays enhanced programming properties and desirable data retention behavior. While no improvement in the erasing efficiency is observed, the JL device still exhibits comparable erase window to the IM counterpart. Consequently, the proposed JL NW structure with complementary metal-oxide semiconductor compatible process appears to be very promising for low-cost and ultrahigh-density NVMs for future 3-D electronics and SOP applications.
The authors would like to thank National Nano Device Laboratories and Nano Facility Center of National Chiao Tung University for their assistance in device fabrication. This work was supported in part by the Ministry of Education in Taiwan under Aim for the Top University Program, and in part by the National Science Council of the Republic of China under contract no. 99-2221-E-009-167-MY3.
- Kamigaki Y, Minami S, Hagiwara T, Furusawa K, Furuno T, Uchida K, Terasawa M, Yamazaki K: Yield and reliability of MNOS EEPROM products. IEEE J Solid-State Circuits 1989, 24: 1714. 10.1109/4.45010View ArticleGoogle Scholar
- Lee JD, Hur SH, Choi JD: Effects of floating-gate interference on NAND flash memory cell operation. IEEE Electron Device Lett 2002, 23: 264.View ArticleGoogle Scholar
- White MH, Adams DA, Bu J: On the go with SONOS. IEEE Circuits Devices Mag 2000, 16: 22. 10.1109/101.857747View ArticleGoogle Scholar
- Khomenkova L, Sahu BS, Slaoui A, Gourbilleau F: Hf-based high-κ materials for Si nanocrystal floating gate memories. Nanoscale Research Lett 2011, 6: 172. 10.1186/1556-276X-6-172View ArticleGoogle Scholar
- Sahu BS, Delachat F, Slaoui A, Carrada M, Ferblantier G, Muller D: Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiNx:H films. Nanoscale Research Lett 2011, 6: 178. 10.1186/1556-276X-6-178View ArticleGoogle Scholar
- Walker AJ, Nallamothu S, Chen EH, Mahajani M, Herner SB, Clark M, Cleeves JM, Dunton SV, Eckert VL, Gu J, Hu S, Knall J, Konevecki M, Petti C, Radigan S, Raghuram U, Vienna J, Vyvoda MA: 3D TFT-SONOS memory cell for ultra-high density file storage applications. VLSI Symp Tech Dig 2003, 2003: 29.Google Scholar
- Lai EK, Lue HT, Hsiao YH, Hsieh JY, Lee SC, Lu CP, Wang SY, Yang LW, Chen KC, Gong J, Hsieh KY, Ku J, Liu R, Lu CY: A highly stackable thin-film transistor (TFT) NAND-type flash memory. VLSI Symp Tech Dig 2006, 2006: 46.Google Scholar
- Lue HT, Hsu TH, Hsiao YH, Hong SP, Wu MT, Hsu FH, Lien NZ, Wang SY, Hsieh JY, Yang LW, Yang T, Chen KC, Hsieh KY, Lu CY: A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. VLSI Symp Tech Dig 2010, 2010: 131.Google Scholar
- Hsu HH, Lin HC, Luo CW, Su CJ, Huang TY: Impacts of multiple-gated configuration on the characteristics of poly-Si nanowire SONOS devices. IEEE Trans. Electron Devices 2011, 58: 641.View ArticleGoogle Scholar
- Su CJ, Tsai TI, Liou YL, Lin ZM, Lin HC, Chao TS: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett 2011, 32: 561.Google Scholar
- Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R: Nanowire transistors without junctions. Nature Nanotechnol 2010, 5: 225. 10.1038/nnano.2010.15View ArticleGoogle Scholar
- Lacy F: Developing a theoretical relationship between electrical resistivity, temperature, and film thickness for conductors. Nanoscale Research Lett 2011, 6: 636. 10.1186/1556-276X-6-636View ArticleGoogle Scholar
- Björk MT, Schmid H, Knoch J, Riel H, Riess W: Donor deactivation in silicon nanostructures. Nature Nanotechnol 2009, 4: 103. 10.1038/nnano.2008.400View ArticleGoogle Scholar
- Fernández-Serra MV, Adessi C, Blasé X: Surface segregation and backscattering in doped silicon nanowires. Phys Rev Lett 2006, 96: 166805.View ArticleGoogle Scholar
- Su CJ, Liou YL, Tsai TI, Lin HC, Huang TY: Fabrication and characterization of junctionless poly-Si nanowire devices with gate-all-around structure. IEEE Silicon Nanoelectronics Workshop 2011, 2011: 25.Google Scholar
- Lenzlinger M, Snow EH: Fowler-Nordheim tunneling into thermally grown SiO2. J Appl Phys 1969, 40: 278. 10.1063/1.1657043View ArticleGoogle Scholar
- Fu J, Jiang Y, Singh N, Zhu CX, Lo GQ, Kwong DL: Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture. IEEE Electron Device Lett 2009, 30: 246.View ArticleGoogle Scholar
- Hung MF, Wu YC, Tang ZY: High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory. Appl Phys Lett 2011, 98: 162108. 10.1063/1.3582925View ArticleGoogle Scholar
- Lee CH, Choi KI, Cho MK, Song YH, Park KC, Kim K: A novel SONOS structure of SiO2/SiN/A12O3with TaN metal gate for multi-giga bit flash memories. IEDM Tech Dig 2003, 2003: 613.Google Scholar
- Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP: Performance estimation of junctionless multigate transistors. Solid-State Electronics 2010, 54: 97. 10.1016/j.sse.2009.12.003View ArticleGoogle Scholar
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