A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires
© Su et al; licensee Springer. 2012
Received: 30 November 2011
Accepted: 29 February 2012
Published: 29 February 2012
In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.
KeywordsJL; NW poly-Si SONOS TFT
With the proliferation of portable electronic products, the demand of high density nonvolatile memories [NVMs] has boosted tremendously. Among various nonvolatile memory [NVM] architectures, the flash memory, based primarily on floating-gate [FG] devices, has dominated the mainstream NVM market for decades. FG devices, however, are inherently vulnerable to fatal data loss through a single defect in the tunnel oxide , and face stringent challenges in the course of device downscaling owing to the gate-coupling concern . In light of this, flash memory based on charge trapping [CT] devices, such as silicon-oxide-nitride-oxide-silicon [SONOS] multilayer structure  and its various derivatives [4, 5], has received renewed interest, and is extensively investigated recently. Being inherently immune to gate-coupling issue and more tolerant to the defects in the thin tunnel oxide, a SONOS memory device enables thinner gate stack height for stronger electrostatic control, and thus is more scalable. Concurrently, flash memory constructed on polycrystalline silicon thin-film transistors (poly-Si [TFTs]) has attracted enormous attention owing to the low-cost and low-temperature fabrication processes and its compatibility with system-on-panel [SOP] or system-on-chip integration [6, 7]. In addition, a thin-film transistor [TFT]-SONOS array is also attractive for three-dimensional [3-D] multilayer stack structure for the purpose of ultrahigh memory cells density without aggressive scaling of device dimensions . However, due to the grainy structure and defects associated with grain boundaries in the films, typical poly-Si TFT-based memory devices face some challenging issues, such as poor subthreshold swing [SS] and slow memory operation speed. Nevertheless, by employing nanowire [NW] channels with multiple-gated configuration in TFTs, the memory speed and subthreshold swing have been demonstrated to be significantly improved, thanks to better gate controllability and reduced defects in the small volume of NWs . Recently, we have developed a junctionless [JL] poly-Si NW transistor with enhanced drive current and reduced source/drain [S/D] series resistance using in situ heavily doped poly-Si . Such material features uniform doping concentration and is commonly used for gate electrode in the fabrication of field-effect transistors [FETs]. A JL transistor features the same doping polarity and concentration throughout the entire device, and thus alleviates the requirement of precise control of dopant distribution in the S/D regions . In this work, we further apply and investigate such scheme to SONOS flash memory device for the purpose of reducing the fabrication complexity and enhancing the programming efficiency by taking advantage of the higher carrier concentration in the JL NW channels.
Device fabrication and experiment
Results and discussion
In summary, we have successfully demonstrated the feasibility of JL NW SONOS memory device by employing only one in situ-doped n+-poly-Si layer. In addition to the much simplified fabrication process, the fabricated device displays enhanced programming properties and desirable data retention behavior. While no improvement in the erasing efficiency is observed, the JL device still exhibits comparable erase window to the IM counterpart. Consequently, the proposed JL NW structure with complementary metal-oxide semiconductor compatible process appears to be very promising for low-cost and ultrahigh-density NVMs for future 3-D electronics and SOP applications.
The authors would like to thank National Nano Device Laboratories and Nano Facility Center of National Chiao Tung University for their assistance in device fabrication. This work was supported in part by the Ministry of Education in Taiwan under Aim for the Top University Program, and in part by the National Science Council of the Republic of China under contract no. 99-2221-E-009-167-MY3.
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