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Figure 4 | Nanoscale Research Letters

Figure 4

From: Ferroelectric memory based on nanostructures

Figure 4

Schematic circuit diagram of In 2 O 3 nanowire FeFET (a) and characteristics of PZT-gated In 2 O 3 NW transistor (b). The PZT-gated In2O3 NW transistor with VDS = −0.1 V shows pronounced hysteresis. ‘1’ and ‘0’ denote two states at VG = 0 V for the memory operation.

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