Figure 4From: Ferroelectric memory based on nanostructuresSchematic circuit diagram of In 2 O 3 nanowire FeFET (a) and characteristics of PZT-gated In 2 O 3 NW transistor (b). The PZT-gated In2O3 NW transistor with VDS = −0.1 V shows pronounced hysteresis. ‘1’ and ‘0’ denote two states at VG = 0 V for the memory operation.Back to article page