Formation of silicon nanostructures with a combination of spacer technology and deep reactive ion etching
© Bien et al.; licensee Springer. 2012
Received: 16 April 2012
Accepted: 24 May 2012
Published: 6 June 2012
A new method of fabricating high aspect ratio nanostructures in silicon without the use of sub-micron lithographic technique is reported. The proposed method comprises two important steps including the use of CMOS spacer technique to form silicon nitride nanostructure masking followed by deep reactive ion etching (DRIE) of the silicon substrate to form the final silicon nanostructures. Silicon dioxide is used as the sacrificial layer to form the silicon nitride nanostructures. With DRIE a high etch selectivity of 50:1 between silicon and silicon nitride was achieved. The use of the spacer technique is particularly advantageous where self-aligned nanostructures with potentially unlimited lengths are formed without the need of submicron lithographic tools and resist materials. With this method, uniform arrays of 100 nm silicon nanostructures which are at least 4 μm tall with aspect ratio higher than 40 were successfully fabricated.
As microdevices shrinks towards nanoscale, formation of high aspect ratio nanostructures will be more challenging. These nanostructures has numerous applications such as photonic crystals[1, 2], thermoelectric generators, sensors, resonators, nanocapacitors and nano-molds for nanoimprint lithography. The aspect ratio of the device is defined by the depth to width ratio of the structure.
Typically, in semiconductor device fabrication, a combination of sub-micron lithography techniques and etching are commonly used in generating patterns with nano dimensions. Such techniques includes electron beam lithography, dip-pen lithography, near field scanning probe lithography, nanoimprint lithography and x-ray lithography. However, these techniques might not be suitable to produce high aspect ratio nanostructures as there is resist imposed limitations during etching, namely the resist thickness is thin and unable to withstand long durations of high power plasma etching. Alternatively, silicon nanostructures or nanowires can also be synthesized by bottoms-up method via chemical vapour deposition, laser-ablation and thermal evaporation techniques. However, organising these nanowires into ordered arrays is challenging and the synthesis process often requires the use of metal catalyst or nano-powders which are not compatible with the standard CMOS fabrication processes.
In this letter, we demonstrate a new method of forming high aspect ratio silicon nanostructures, where very accurate alignment of the nanostructures can be achieved because the alignment is not determined by the lithographic tool but by the spacer technique used. The fabrication method is divided into two parts where arrays of silicon nitride nanostructures are first formed by the CMOS spacer method which is typically used in the fabrication of nanometer transistors. The formed nitride nanostructured arrays are then used as a masking layer during the silicon etching process. To produce an array of silicon nanostructures, we etch the silicon substrate in an inductively coupled plasma, Tegal AMS 110 DRIE system. Further details are described in the following methodology and results sections.
DRIE of silicon with SF 6 and C 4 F 8 plasma
Silicon Etch Rate
Results and discussions
Besides having high aspect ratio nanostructures, very accurate structure alignment are achieved because the structure alignment is not determined by lithographic tool but by the spacer method, where the length of the fabricated structures can be unlimited. With the spacer method, dimensions as fine as 10 nm can be achieved. However, there is a dimension limitation during the silicon etch with SF6 and C4F8 plasma as the etch process would typically create sidewall scalloping greater than 10 nm. Further etching of silicon nitride in buffered HF can further reduce the width of the nanostructures, where the lower limit of the achievable width of the nanostructures is dependent on the silicon dioxide thickness, silicon nitride thickness, uniformity of the nitride coverage and directionality of the etch process. It is also possible to reduce the dimensions of the nanostructures through lateral isotropic plasma etching of the nitride spacers where the process can be controlled by varying the etch recipes used which is dependent on gas ratios, chamber pressure and rf power. However, to achieve accurate directional control is difficult and the etch rate of nitride can still be high. With wet etching, the etch rate of nitride in buffered HF was found to be only 2 nm/min which allows better control of the final nitride dimensions.
In summary, we have demonstrated a method of fabricating high aspect ratio nanostructures in silicon using a combination of CMOS spacer method to form silicon nitride nanostructure masking and deep reactive ion etching of silicon with SF6 and C4F8 plasma for applications in photonics, photovoltaic and nano-electromechanical (NEM) devices. The demonstrated fabrication method is cost effective where it does not require the use of sub-micron lithographic tools and techniques. Alignment of the silicon nitride nano-masking can be controlled accurately and the final silicon nanostructures formed are of aspect ratio higher than 40 which is significantly higher than that produced previously for nanostructures. In this work, etch selectivity between silicon and silicon nitride of approximately 50:1 was achieved and the authors believe that the dimensions of the nanostructures can be further reduced by thinning the silicon nitride nano-masking in buffered hydrofluoric acid solution.
This research was supported by eScience funding 01-03-04-SF0027 and National Nanotechnology Directorate funding NND/ND/(2)/TD11-012 under the Ministry of Science, Technology and Innovation (MOSTI), Malaysia.
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