Figure 3From: Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique52° tilted SEM images of different sized NW devices before the gate stack formation. (a) A tiny NW device showing NWs exposed on both sides of the temporary dielectric step, (b) a mid-sized NW device, and (c) a large-sized NW device.Back to article page