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Figure 6 | Nanoscale Research Letters

Figure 6

From: Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique

Figure 6

On currents and 52° tilted SEM image of a NW device. (a) On currents, extracted at VGVth = 2 V and VD = 0.5 V, as a function of channel length for DC and UC devices. (b) 52° tilted SEM image of a NW device with L = 5 μm showing collapse of NWs in the central channel region. The inset shows a NW device with L = 1 μm depicting normal suspension of NWs between the S/D regions.

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