Figure 7From: Excellent resistive memory characteristics and switching mechanism using a Ti nanolayer at the Cu/TaOx interfaceTypical I-V hysteresis loop of S1 and S2 devices and cumulative probability of leakage currents. Typical I-V hysteresis loop with 100 consecutive cycles under a CC of 500 μA for (a) S1 and (b) S2 devices. (c) Cumulative probability of leakage currents for S1 and S2 devices.Back to article page