- Nano Express
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Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography
© Dehzangi et al.; licensee Springer. 2012
- Received: 23 March 2012
- Accepted: 29 June 2012
- Published: 11 July 2012
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.
- Atomic force microscopy
- Junctionless transistors
- Local anodic oxidation
- Double gate
- Single gate junctionless silicon nanowire transistor
The aggressive trend of scaling transistors requires a new and more effective device to catch up with this rapid trend for modern transistors. Several innovations in fabrication process such as high κ dielectrics , metal gate electrodes , stressors , and new transistor architectures based on silicon-on-insulator (SOI) such as Fin field-effect transistors (FETs) , multigate FETs , omega-gate FETs , gate-all-around FETs , or developed non-epitaxial raised metal Schottky source drain  have been introduced. In the recent years, junctionless transistors (JLTs) appeared to be the promising alternative for new generation of transistors . All existing transistors contain semiconductor junctions. Contemporary transistors with ultrasmall size need ultrasharp doping concentration gradients in junctions. The doping must switch from ultra high concentration n-type to p-type along the very small area in size of some nanometers, which imposes severe limitations on the processing thermal budget and requires the development of costly millisecond annealing techniques. In JLT the doping concentration in the channel source and drain is uniform with high concentration profile for the channel in order to have a reasonable amount of current flow when the device is turned on . The lack of doping concentration gradients provides the smaller size and cancels the need for costly ultrafast annealing techniques. In the last two years, the research in JLTs was focused in design and property [11–13], simulation [14–16], high temperature performance , and new fabrication method with higher mobility and better performance [18–20].
The principle of atomic force microscopy (AFM) nanolithography, using local anodic oxidation (LAO) on SOI, has been described for the first time by Snow and Campbell et al. [21, 22], and they astutely expanded AFM nanolithography for fabrication of nanostructures. Ionica et al.  have remarkably reported the electrical characteristics of the devices made by AFM nanolithography. In the recent years, some new works have been performed to improve the method of AFM nanolithography [24, 25]. However, the lack of sufficient explanation or interpretation for the behavior of these structures is still an interesting issue and worth for further investigation. In fact, fabrication of nanotransistors by AFM nanolithography with similar structure has been developed with prominent result in the last decade, but recent rising of the JLTs theory and fabrication can bring up the AFM nanolithography as the extra alternative. We already reported the fabrication of the p-type single gate (SG) JLT device with a simple structure, low doping concentration, and no gate oxide layer [26–29]. The most important advantage of AFM nanolithography is that it impedes damage of the crystalline structure of silicon due to highly energetic electrons which are normally introduced to the structure by techniques such as electron beam lithography.
In this paper we report the fabrication of a double gate structure with improved method by implementing the advantages of AFM nanolithography in contact mode with a simple structure. We used the SOI technology to ensure a very sharp interface top silicon layer-silicon dioxide and used buried oxide layer as an etch stop layer during fabrication. Low doping concentration p-type SOI was used in order to have less scattering effect and low ‘off’ current. Also, the electrical property of both double gate (DG) and single gate JLT will be compared; the charge transmission, according to the JLTs’ principal with the glance of accumulation mode transistors function, will be investigated.
Local anodic oxidation
Wet etching process
KOH wet etching is a very significant part in the fabrication of SG and DGJLT. In fact, having contamination, ill-etched, or over etching structures were hardly avoidable in wet etching which, accordingly, the accuracy and precaution are important. To remove the undesired Si area, KOH was used as an etchant. The KOH concentration also affects the quality of the etched surface. Referring to the previous reports in KOH wet etching [33–37], we used a 30 wt.% KOH solution, saturated with isopropyl alcohol (IPA) at 63°C to remove all the non-protected silicon areas. IPA was used in this work as initiator to improve the cleaning process providing smooth surface. IPA reduces the etch rate, hence improving the surface roughness and making the etching process more controllable. The best optimized condition was the solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63°C, immersing time for 20 s, and stirring at 600 rpm. The stirring of the solution is to ensure the uniformity of the etching process.
The final structure was obtained by removing the oxide layer using HF acid (Figure 3b,d). In fact, several models have been proposed for the silicon anisotropic etching mechanism in aqueous KOH, which we have chosen as the method by considering of the crystallographic planes for a cubic crystal. In a cubic crystal, the (110) plane is normal to the diagonal of a surface plane, and the (111) plane is normal to a volume diagonal. For the atoms located on the (100) plane, they have two dangling bonds and two bonds remaining in the crystal. Like in our case, when a (100) plane is exposed by the etching solution, OH− can attach to the dangling bonds and loosen the other bonds, so they can break easily. The KOH etching of (100)-oriented silicon provides V-shaped grooves .
In Figure 6a, we can recognize the effect of the gate on channel in a DG structure which is more effective than SG due to the asymmetry of SG. In the DG structure the pinch off effect was achieved in VG = +2, while this value cannot provide the same current value in SG. This required higher voltage to approach pinch off effect in SG structure which was in VG = +3 V (Figure 5). Figure 6b shows the drain conductance for SG and DG structures under the different gate voltage. By increasing the gate voltage, the drain conductance for both structures will be decreased. For comparing DG structure to SG device, we have a more effective gate voltage in the channel approaching the pinch off effect (off state) with lowest drain conductance, which is consistent to the output characteristics and our expectation about the DG structure. The trend for drain conductance is the same with MOSFETs  and JLTs , yet the slope is smaller here which can be explained by low doping concentration and current value.
Although the SS value is relatively higher than the best value in single crystal silicon devices  and recent JLTs [20, 43, 44], it is still comparable with the lowest reported value of vertical silicon nanowire array devices . In general, the degradation of SS is due to the increase in the interface state density, decrease of oxide capacitance, and increase in the doping concentration of metal oxide silicon transistor’s channel . However, in our work the interface state density probably cannot play an important role since we have only one interface with the channel (channel/BOX interface), and the current value is low. The most important reason for higher SS value in our case could be explained by the lack of oxide layer between the gate and the channel. It lacks the fixed potential drop in cross section of the nanowire (perpendicular to the current flow), which is necessary for inducing sufficient potential to change current linearly with the gate voltage . In SGJLT device, the asymmetry of the gate location provides higher SS value compare to DGJLT device with the symmetric gate locations.
In recent reports on experimental JLTs [18, 47], we did not encounter any case of on state condition under the zero gate voltage due to having an opposite doping concentration for the gate and the channel, unless for the simulation cases and for very small gate lengths . The charge transmission in DG and SGJLT operates quite differently from the conventional MOSFETs and also slightly different from the JLT description in recent literature. The devices are working in on state for nonzero VDS and VG = 0 V. The reason can arise from the fact that the field effects from the different work function of the gate and channel cannot cause the device to be turned off at VG = 0 V due to the same doping concentration of the channel and gate contact, and no oxide layer for the gate.
Basically, regardless of the gate work function difference between the gate electrode and channel, JLTs are ‘gated resistor’ which is in the on state at VG = 0 V . According to the JLT’s principal, when the device is turned on, it approaches the flat band condition. It basically behaves as a resistor, and the electric field perpendicular to the current flow is equal to zero in the ‘bulk’ channel. In fact, as the advantage of our fabrication method, the AFM lithography keeps the surface and the body of the upper Si layer of the SOI intact and untouched. So we expect to find more bulk property, for example, higher mobility and less surface scattering effect for the channel under the gate.
However, by negatively raising the gate voltage, it is probable to have a little increasing of the current due to some accumulated charges, which were injected from the source (region I) to the channel (red color areas in Figure 7). The drain current mainly flows through a bulk channel. An additional small conduction likely originated from a lightly accumulated channel in sidewalls facing the gates, when the gate voltage is large enough. The influence of the gate on the channel is not very effective to induce an accumulation mode due to the device configuration, low doping concentration, and the lack of oxide layer between the gate and the channel. Accordingly, increasing the gate voltage cannot help to make an effective accumulation layer and we do not expect to have the accumulation mode for high gate voltage. Normally in high doping JLTs in on state, after increasing the gate voltage, the device is able to be converted into the accumulation mode with significant increasing of the current (mostly is not desired to reach) [9, 47]. Actually, another reason that we interpret the devices as JLT and not in accumulation mode is the ineffective negative increasing gate voltage on the channel.
In the on state condition, for a given VDS, the electric field from the source to the negatively biased drain must be significantly small (nearly zero) in the neutral wire at the center of the channel. In the linear region we expect that the negative charge in region I (Figure 7), which is adjacent to the area of I/II interface, should be gathered. This charge in the p-type material can only come from depletion in the channel in linear region.
This equation can be compared with the general expression of drain current for conventional MOSFETs in the saturation region or even in the accumulation mode . In addition, because of the presence of ohmic contacts for the majority carriers and their location, which is away from the channel edges, we will not have any ambipolar behavior. Unfortunately, the transistors showed leakage through the gate electrode when gate voltages exceeded −3 V. However, the device worked was acceptable for gate voltages smaller than −3 V and gave us some information to confirm our simple model.
The DG and SGJLT were fabricated by AFM-LAO nanolithography on low doped p-type SOI, followed by two improved wet etching process. We do not have a conventional situation for above the threshold voltage and channel saturation, since the devices are gated resistor and on state pinch off transistor. Then negative VG cannot provide the accumulation in channel, but the pinch off occurs alike in a regular junctionless field-effect transistor. The output and transfer characteristic comparison of DG and SG structures were shown and the simple model according to the JLT principal.
The authors gratefully acknowledge that this work was financially supported by the Science Fund from the Ministry of Science, Technology and Innovation (MOSTI), Malaysia, under project no. 03-01-05-SF0384, the USM Short Term Grant under project number 304/PBAHAN/6039035, and UPM FRGS number 5524051.
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