Table 3 45-nm process propagation delay computation between CNTFET (with and without interconnect) and MOSFET (post-layout simulation)
Logic circuits | CNTFET with 45-nm process design guidelines | MOSFET with 45-nm process | |
|---|---|---|---|
Delay without interconnects | Delay with 5-μm interconnect | Delay (post-layout simulation) | |
Propagation delay, | Propagation delay, | Propagation delay, | |
t p(ps) | t p(ps) | t p(ps) | |
NOT | 0.14 | 9.277 | 5.005 |
NAND2 | 0.39 | 12.97 | 8.719 |
NAND3 | 0.61 | 16.87 | 11.343 |
NOR2 | 0.47 | 12.98 | 8.797 |
NOR3 | 0.50 | 16.48 | 11.655 |