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Figure 1 | Nanoscale Research Letters

Figure 1

From: Resistive switching of Au/ZnO/Au resistive memory: an in situ observation of conductive bridge formation

Figure 1

Schematics of the TEM chip fabrication. (a) Deposition of 80/20-nm Si3N4/SiO2 on Si substrate by LPCVD,(b) KOH chemical etching from the back side of the Si substrate, followed by deposition of 25-nm-thick ZnO layer by radio frequency magnetron sputtering, (c) E-beam lithography of PMMA to define position of the electrodes, (d) deposition of Au by metal deposition and lift-off processes, e) detailed configuration of the TEM chip after fabrication, and (f) the corresponding SEM and TEM images of the device.

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