- Nano Express
- Open Access
Non-oxidized porous silicon-based power AC switch peripheries
© Menard et al.; licensee Springer. 2012
- Received: 27 April 2012
- Accepted: 19 September 2012
- Published: 11 October 2012
We present in this paper a novel application of porous silicon (PS) for low-power alternating current (AC) switches such as triode alternating current devices (TRIACs) frequently used to control small appliances (fridge, vacuum cleaner, washing machine, coffee makers, etc.). More precisely, it seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device. Based on the technological aspects of the most commonly used AC switch peripheries physically responsible of the TRIAC blocking performances (leakage current and breakdown voltage), we suggest to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles. Then, we comment the voltage capability of practical samples emanating from the proposed architecture. Thanks to the characterization results of simple Al-PS-Si(P) structures, the experimental observations are interpreted, thus opening new outlooks in the field of AC switch peripheries.
- Anodic etching
- Meso- and microporous silicon
- AC switch periphery
- Electrical characterization
Up to now, porous silicon is widely investigated for sensing, photonic, or MEMS applications as it is well summarized in, but its mesoporous or microporous electrical properties are not massively exploited. Two main topics have been discussed in the literature. First, the integration of inductances on the top of micro- or mesoporous layers improves their quality factor by lowering Eddy currents in the substrate. Second, the isolation of silicon islands, where bipolar or MOS transistors may be integrated, has been studied in[3–5] for the development of a novel integrated circuit technology. However, most of the time, porous silicon is oxidized in order to improve its dielectric performances.
Nevertheless, several research teams have demonstrated that depending on bulk properties and anodic etching conditions, porous silicon behaves like an insulator. More precisely, its porosity is higher and its dielectric constant and conductivity are lower as illustrated in[6, 7]. It should be noted too that high porosities generate a thermal activation increase of the porous silicon conductivity.
High porosities (>50%) may be reached through p-type substrates with doping levels between 1016 and 1018/cm3 as explained in. Then, knowing that such p-type layers may be easily found in power alternating-current (AC) switch technologies, and knowing that insulation is one of the major issues of this kind of structures, it is interesting to study how porous silicon may bring improvements for such devices.
The first part of the present paper will remind the most important features to know about AC switches and their associated technologies. We will also give the first schematic of the novel AC switch architecture that we would like to target. Then, we will describe our experimental structure, on which electrical assessments have been performed. Finally, the results will be discussed on the basis of previous observations done on simple vertical metal-porous silicon-silicon (metal-PS-Si(P)) structures.
AC switch peripheries: state of the art
Usually, the name of the technology corresponds to the way the periphery is achieved. In the case of the double mesa, grooves are etched from the n-type silicon substrate (Nbulk) on both sides of the die. They are then filled with glass, the most appropriate material when thick passivation layers are needed. For the top glass, deep p-wells are diffused from both sides of the wafer and joined to form through wafer p-wells (Piso). The insulation is then ensured by top side grooves filled with glass. The structure of the planar periphery is based on the top glass one, except that the p+ doping of the active area is localized through a standard photolithography step, thus allowing the use of thinner passivation layers.
Then, anodic etching was carried out on top of the wafer in a 6-in. double-tank anodization cell filled with a 30% HF-H2O-acetic acid electrolyte, applying a constant current density of 30 mA/cm2 for 60 min. Even if the cell allows 6-in. treatments, the anodization here was restricted to a 1-in. circular surface. After etching, the wafer was dried at 150°C for a few minutes in an ambient atmosphere.
The breakdown capability of the porous silicon layer obtained from the samples described previously was assessed on a probe station connected to a Tektronix 370A curve tracer (Tektronix Ltd., Bracknell, UK). A metallic chuck is used in order to connect the back side of the wafer, and one probe is positioned on top. Note that no metal layer was used to facilitate the electrical contact as it was not supposed to impact the results as discussed in the ‘Results and discussion’ section. All measurements were carried out at ambient temperature and in the dark. Figure7 depicts the experimental setup and typical electrical results in both forward and reverse biases. At a current level of 1 μA, a usual reference value for AC switches, the porous silicon structure demonstrates voltage capabilities higher than 520 and 350 V with positive and negative biases, respectively. In parallel, some samples coming from the same experimentation but without any porous silicon layers were tested with voltage results lower than 30 V at 1 μA. The insulation character of the porous silicon layer is then confirmed.
Despite the simplicity of the structure (large surface pattern, no PS localization, no specific treatment of the porous silicon layer, no metal contact, no passivation layers), interesting voltage blocking capabilities have been reached without any sample destruction and with good reproducibility. Another interesting point is the non-symmetric behavior between forward and reverse biases.
Process conditions and electrical I - V results found in different electrical studies of vertical metal-PS-Si(P) structures
PS contact (according to the authors)
Ben-Chorin et al.
HF (49%) + ethanol (1:1)
3 to 5
0.5 to 15
Au NiCr In
Ben-Chorin et al.
HF (49%) + ethanol (1:1)
3 to 5
0.5 to 15
Au NiCr In
Balagurov et al.
HF (48%) + ethanol (5:1)
1.5 to 30
Bouaïcha et al.
HF (40%) + ethanol (1:1)
2 to 5
Remaki et al.
HF (50%) + ethanol (2:1)
1 to 10
Anderson et al.
30 to 40
0.5 to 5
Anderson et al.
0.01 to 0.03
0.5 to 5
Pulsford et al.
HF + H2O + ethanol (2:3:5)
1.5 and 135
Ca Mg Sb Au Ag
Stievenard and Deresmes
HF (40%) + ethanol (1:1)
Islam et al.
6 to 10
HF (48%) + ethanol (1:1)
30 to 50
This above discussion is easily understandable for columnar pores. If a different pore morphology is achieved, for equivalent PS porosities, we may not observe the same phenomenon. Then, the explanations coming from the BC model for higher PS porosities may be more relevant.
Note that Islam et al. proposed another band diagram to describe the band structure of the PS/Si(P) interface. They considered it as a heterojunction. Different working groups have reported such a behavior. For example, based on their photoluminescence measurements, Koshida and Koyama conclude that quantum confinement and/or lattice distortion effects in the PS layer involve a bandgap increase. Even if the BC electrical mechanism does not imply a PS/Si(P) heterojunction, its existence is not questioned, but electrically speaking, the heterojunction may be inactive as the Fermi level is pinned in the energy region of the surface state.
The diode D1 is associated to the PS/Piso interface, where the expected Piso doping should be included between 1 and 100 mΩ cm. Then, the electrical behavior should comply with the BC model as high porosities (>50%) should be reached. The resistance R1 of the PS layer stemming from the Piso anodization will be strongly correlated with D1. Similar to the couple D1/R1, the PS/Pbase interface may be modeled by the diode D2 associated to its serial PS resistance R2 as the Pbase doping is expected to be more resistive compared to the Piso one. We have added a PS resistance R3 corresponding to the interface between the n-type substrate and the PS layer. Indeed, as a Schottky-type behavior is observed for the PS/Si(P) interface, thus the PS/Si(N) one should be ohmic. This latter point will be demonstrated in a subsequent paper. Finally, we define D3 and D4 as the reverse and direct Pbase/Nbulk junctions, respectively. D3 and D4 typical breakdown voltage is about 1 kV with the involved doping profiles and an appropriate junction termination.
Both hypotheses allow us to explain the observed electrical behavior; nevertheless, further investigations will be necessary to clarify the involved physical mechanisms and to adjust the conception of the porous silicon-based AC switch periphery.
We have discussed the possibility of benefiting from the insulating properties of micro/meso porous silicon etching from p-type silicon on AC switch structures. The first results are promising. Indeed, voltage capabilities of about 500 V have been supported by our simplified porous silicon structure, but many further experimentations will be needed before achieving a reliable AC switch device: localization of the porous silicon layer and fabrication of more realistic samples, definition and characterization of specific patterns to better understand electrical properties of all porous silicon layers embedded in the device, and impact of the AC switch applicative environment knowing that porous silicon properties are highly dependent on the ambient atmosphere (reliability meanings).
The authors would like to thank M. Capelle, T. Defforge, V. Grimal, D. Genard, and S. Miredin for their technical support in the sample realization.
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