Characterization of epitaxial GaAs MOS capacitors using atomic layer-deposited TiO2/Al2O3 gate stack: study of Ge auto-doping and p-type Zn doping
© Dalapati et al; licensee Springer. 2012
Received: 24 November 2011
Accepted: 2 February 2012
Published: 2 February 2012
Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic layer-deposited high-k dielectrics (TiO2/Al2O3) and epitaxial GaAs [epi-GaAs] grown on Ge(100) substrates have been investigated. The epi-GaAs, either undoped or Zn-doped, was grown using metal-organic chemical vapor deposition method at 620°C to 650°C. The diffusion of Ge atoms into epi-GaAs resulted in auto-doping, and therefore, an n-MOS behavior was observed for undoped and Zn-doped epi-GaAs with the doping concentration up to approximately 1017 cm-3. This is attributed to the diffusion of a significant amount of Ge atoms from the Ge substrate as confirmed by the simulation using SILVACO software and also from the secondary ion mass spectrometry analyses. The Zn-doped epi-GaAs with a doping concentration of approximately 1018 cm-3 converts the epi-GaAs layer into p-type since the Zn doping is relatively higher than the out-diffused Ge concentration. The capacitance-voltage characteristics show similar frequency dispersion and leakage current for n-type and p-type epi-GaAs layers with very low hysteresis voltage (approximately 10 mV).
In recent years, there had been increasing interest in the introduction of III-V semiconductors as high-mobility channel materials in nanoscale silicon-based [Si-based] complementary-metal-oxide-semiconductor [CMOS] devices [1–7]. This migration from the present strained Si channels is due to two reasons: First, with the replacement of silicon oxide [SiO2] and silicon oxynitride (SiOxNy) by high-permittivity [high-k] dielectrics as the gate insulator [1–8], the choice of a channel material is no longer restricted to Si. Second, the incorporation of appropriate stressors, such as silicon nitride, can enhance both electron and hole mobilities in sub-90-nm devices; there could be scaling limits to such approaches. An inversion n-channel GaAs field effect transistor [FET] with a metal gate high-k dielectric was fabricated on GaAs wafers by de Souza et al. . Ye et al.  characterized the Al2O3/GaAs metal-oxide-semiconductor field effect transistor [MOSFET] and found a very high drain current and a relatively high transconductance. Also, the studies on the effect of the atomic layer-deposited [ALD] Al2O3 blocking layer indicates that it can suppress the growth of an interfacial layer and that the ALD Al2O3 could reduce the formation of native arsenic oxides to below the detection level of X-ray photoelectron spectroscopy .
For high-volume manufacturing, it is of great interest to develop epitaxial III-V high-mobility channel materials on a silicon platform to realize CMOS devices with increased carrier mobility and device flexibility [9–11]. Convergence of the Si and compound semiconductor industries promises the best of both worlds for device manufacturers due to the high performance, flexibility, and enhanced functionality of III-V compounds coupled with the low manufacturing cost and sheer scale of the Si process. In particular, GaAs has received much attention due to its lower effective mass and, hence, an intrinsic superior transport property than Si. Moreover, it is possible to grow epitaxial GaAs [epi-GaAs] on a Si-based CMOS technology-compatible Ge substrate since the lattice parameter of GaAs (0.5653 nm) is almost identical to that of Ge (0.5658 nm), and both have similar thermal conductivity . In addition, Ge has the added advantage of having a high hole mobility of 1,900 cm2 V-1 s1 at 300 K which is about four times higher than that of Si . This suggests the possibility of a heterogeneous integration of GaAs n-channel FETs with Ge p-channel FETs on a common Si platform.
One of the key considerations in fabricating a surface channel MOSFET using epi-GaAs is to achieve a good interface quality between the epi-GaAs substrate and gate oxide, which is vital for the device performance . Fortunately, atomic layer deposition provides a unique opportunity to integrate high-quality gate dielectrics on bulk and epi-GaAs [2, 14, 15]. It was observed that ALD Al2O3 provides a better interface with GaAs interface compared with other ALD high-k dielectrics [6, 8]. Although, by continuing effort on surface passivation, it is possible to grow a high-quality interface with low defect density, the hysteresis voltage for ALD high-k/GaAs gate stack is still high [2, 7, 15]. There are some attempts to achieve low hysteresis voltage using ALD SiO2, directly deposited titanium oxide [TiO2], and Si passivation on GaAs substrates [16–19]. On the other hand, GaAs grown at its optimum temperature on Ge will result in high Ge contamination, such as auto-doping and formation of Ge-based complexes, as significant Ge atoms will diffuse into the GaAs epilayer during growth. Chia et al.  suggested that a thin 10-nm AlAs interfacial layer is sufficient to effectively block the out-diffusion of Ge atoms at a high growth temperature of 650°C, eliminating Ge-based complexes and auto-doping effects in the GaAs layer. It is highly desirable to grow p-type epi-GaAs with good structural and electronic qualities for n-MOSFET device applications. However, to the best of our knowledge, there is no report of a metal-oxide-semiconductor [MOS] capacitor using p-type epi-GaAs grown on Ge substrates.
TiO2 [17, 18] gate dielectric provides low hysteresis voltage, and thin ALD Al2O3 is a promising gate dielectric for surface passivation [6, 7] as well as improved interface quality. In this paper, we demonstrate ALD TiO2/Al2O3 gate stack on undoped (which is n-type) and Zn-doped (p-type) epi-GaAs grown by metallorganic chemical vapor deposition [MOCVD] technique. The epi-GaAs device characteristics are compared with that of undoped and Zn-doped epi-GaAs for different concentrations. Further, we have identified the minimum Zn dopant concentration required for p-type epi-GaAs substrates. Electrical and physical analyses and simulation using SILVACO software (SILVACO, Inc., Santa Clara, CA, USA) have also been performed to understand the impact of the material and processing conditions for a high-quality gate stack on epi-GaAs substrates and the impact of Ge diffusion on the performance of MOS characteristics. The surface topography of epi-GaAs and high-k/epi-GaAs surfaces was examined via atomic force microscopy [AFM]. Interfacial reaction of high-k/epi-GaAs and Ge out-diffusion was studied by time of flight secondary ion mass spectrometry [ToF-SIMS] for all the structures. Capacitance-voltage [C-V] and current-voltage [I-V] characteristics were measured using an Agilent 4284A LCR (Agilent Technologies Inc., Santa Clara, CA, USA) and a Hewlett-Packard 4140B semiconductor parameter analyzer (Hewlett-Packard Company, Palto Alto, CA, USA), respectively
MOS capacitors were fabricated on epi-GaAs substrates. The epi-GaAs substrates were grown at 620°C to 650°C by MOCVD technique. Vicinal Ge (100) substrates with 6° offcut toward the (111) plane were used to ensure that the epitaxial GaAs grown on Ge is free from APD defects. Prior to the growth of GaAs layers, the Ge substrate was heated up to and kept at 650°C for 5 min under H2 environment to remove the native oxide layer. Tertiarybutylarsine and trimethylgallium were introduced into the reactor for the growth of the Zn-doped 300-nm-thick GaAs layer at 620°C. For undoped epi-GaAs, the GaAs substrate was grown on Ge(100) samples with an AlAs interfacial layer at 650°C by MOCVD technique. The details of the film growth and their properties are reported elsewhere . The as-grown wafers were then degreased using isopropanol, cleaned in HF solution (1%) for 3 min to remove the native oxide, and then dipped in NH4OH solution for 10 min. A thin layer of Al2O3 was deposited on epi-GaAs using trimethylaluminium (SAFC Hitech, Haverhill, MA, USA; 99.9%) and H2O as the precursors in a viscous flow-type (0.6 Torr working pressure) atomic layer deposition equipment (f·XALD ALD equipment, Azimuth Technologies Pte Ltd., Singapore) with a N2 flow rate of 50 sccm at 170°C. After that, TiO2 films were deposited under similar conditions. Vapors of TiCl4 (Merck & Co., Inc., Whitehouse Station, NJ, USA; 99%) and H2O precursors were sequentially introduced into the chamber with an exposure time of 0.1 s and purged by 50-sccm N2 flow for 10 s between the two exposures. Post-deposition annealing was carried out in a N2 ambient at 500°C for 1 min by rapid thermal annealing technique. The Au metal, deposited by sputtering, was used as the gate electrode (area, 7.8 × 10-3 cm2). Finally, a low-resistance ohmic back contact was formed by depositing Ti/Pt/Au alloy on the p-GaAs substrate, AuGeNi alloy on the n-GaAs substrate, and Au on the Ge substrate.
Results and discussion
It was observed from the SIMS analysis of the epi-GaAs layer grown at 620°C that a significant amount of Ge was diffused into the epi-GaAs thereby converting it to n-type due to auto-doping of Ge to GaAs. By introducing a high density of Zn, it is possible to convert the n-type epi-GaAs to p-type. It is worth noting that although, from SIMS analysis, there was Ge atom diffusion in the epi-GaAs layer up to 20 nm with an AlAs interlayer and up to 100 nm without the AlAs interlayer, however, for both the cases, the epi-GaAs layer shows an n-type behavior. This suggests that although AlAs effectively reduced the Ge atom diffusion into GaAs, there is still some Ge which could possibly be below the SIMS detection limit. From the simulation of Ge diffusion and C-V characteristics, it was also observed that Ge atoms were present in the epi-GaAs even for the AlAs barrier layer, but the concentration is very low (approximately 1015 cm-3). The hysteresis voltage for ALD TiO2/Al2O3 gate stack was very low (approximately 10 mV) as shown in the inset of Figure 4.
In summary, epi-GaAs MOS capacitors were fabricated and characterized using electrical and physical analysis. Atomic layer-deposited TiO2/Al2O3 gate stack is used to fabricate epi-GaAs MOS capacitors on a Ge substrate for III-V CMOS applications. The epi-GaAs MOS capacitor shows an nMOS behavior for undoped and even for Zn-doped epi-GaAs with low concentration due to Ge auto-doping, which is confirmed by the SIMS analysis and simulation. Zn-doped epi-GaAs with a high concentration > 1018 cm-3 converts epi-GaAs into p-type. Interfacial reaction mechanisms between epi-GaAs and ALD TiO2/Al2O3 have been discussed through SIMS analysis and capacitance-voltage characteristics. Although the simulated and experimentally obtained C-V result showed frequency dispersion due to the presence of the interfacial lossy dielectric layer between Al2O3 and epi-GaAs, the hysteresis voltage for epi-MOS device is very small for the ALD Al2O3/TiO2 gate stack. Therefore, using suitable surface passivation with ALD TiO2/Al2O3 on epi-GaAs can pave the way for the next generation of Si-based CMOS technology for ultrahigh-speed devices or multifunctional devices on a Si platform.
One of the authors, A. Das, would like to acknowledge the Department of Science and Technology (DST), India, for providing the Inspire Fellowship scholarship to pursue her research work.
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