Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory
© Yeh et al.; licensee Springer. 2013
Received: 5 June 2013
Accepted: 10 July 2013
Published: 22 July 2013
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.
Electrically erasable programmable read-only memory (EEPROM), which is a kind of nonvolatile memory (NVM) [1, 2], has been widely used in portable products owing to its high density and low cost . Embedded EEPROM that is based on poly-Si thin film transistor (TFT) has attracted much attention because it can meet the low-temperature process requirement in thin film transistor liquid crystal display applications [4, 5]. However, since the process and physical limitations of the device limit the scaling of the flash NVM that is based on a single-crystalline Si substrate, according to Moore’s law, the three-dimensional (3D) multi-layer stack memory provides a high-density flash memory solution. The poly-Si-based NVM also has great potential for realizing 3D high-density multi-layer stack memory [6–8]. A planar EEPROM that uses twin poly-Si TFTs has also been developed for the above aforementioned applications [4, 9]. The advantages of this twin TFT structure include processing identical to that of a conventional TFT, which is easily embedded on Si wafer, glass, and flexible substrates. Additionally, the low program/erase (P/E) operating voltage of this planar NVM can be easily obtained by increasing the artificial gate coupling ratio (αG).
Recently, several investigations have demonstrated that gate control can be substantially enhanced by introducing a multi-gate with a nanowire (NW) structure [10–12]. In our previous works [13, 14], NWs were introduced into twin poly-Si TFT NVM to increase P/E speed. However, reducing the P/E voltage while ensuring the reliability of this device remains a challenge.
Therefore, in this work, to reduce the P/E voltage, we try to use p-channel devices with band-to-band tunneling-induced hot electron (BBHE) operation compared with Fowler-Nordheim (FN) operation and use a Ω-gate structure to have little deterioration. These p-channel twin fin field-effect transistor (FinFET) EEPROM devices with a Ω-gate structure have excellent retention and endurance.
These devices were fabricated by initially growing a 400-nm-thick thermal oxide layer on 6-in. silicon wafers as substrates. A thin 50-nm-thick undoped amorphous Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. The deposited a-Si layer was then solid-phase-crystallized at 600°C for 24 h in nitrogen ambient. The device’s active NWs were patterned by electron beam (e-beam) direct writing and transferred by reactive-ion etching (RIE). Then, they were dipped into HF solution for 60 s to form the Ω-shaped structure. For gate dielectric, a 15-nm-thick layer of thermal oxide was grown as tunneling oxide. Then, a 150-nm-thick poly-Si layer was deposited and transferred to a floating gate by electron beam direct writing and RIE. Then, the T1 and T2 self-aligned P+ source/drain and gate regions were formed by the implantation of BF2 ions at a dose of 5 × 1015 cm−2. The dopant was activated by ultrarapid thermal annealing at 1,000°C for 1 s in nitrogen ambient. Then, a 200-nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD. Next, the contact holes were defined and 300-nm-thick AlSiCu metallization was performed. Finally, the devices were then sintered at 400°C in nitrogen ambient for 30 min.
To maximize the voltage drop in the tunnel oxide of T1, the gate capacitance of T2 (C2) must exceed the gate capacitance of T1 (C1). Hence, the NVM device with a high αG exhibits a high P/E speed and can be operated at a low voltage. In this work, the devices were designed to have a coupling ratio of 0.85, which is extremely high for memory applications.
Results and discussion
This work developed a novel Ω-gate NW-based twin poly-Si TFT EEPROM. Experimental results demonstrated that the Ω-gate NW-based structure had a large memory window and high P/E efficiency because of its multi-gate structure and even oxide electrical field at the NW corners. After 104 P/E cycles, ΔVth = 3.5 V (72.2%). The proposed twin-TFT EEPROM with a fully overlapped control gate exhibited good data endurance and maintained a wide threshold voltage window even after 104 P/E cycles. This Ω-gate NW-based twin poly-Si TFT EEPROM can be easily incorporated into an AMLCD array press and SOI CMOS technology without any additional processing.
The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under contract no. NSC 101-2221-E-007-088-MY2. The National Nano Device Laboratories is greatly appreciated for its technical support.
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