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# Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

*Nanoscale Research Letters*
**volume 8**, Article number: 454 (2013)

## Abstract

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

## Background

Memristors are being intensively explored as possible candidate for future memories because of simplicity in fabrication, possibility in three-dimensional integration, compatibility with (complementary metal-oxide-semiconductor) CMOS technology in the fabrication process, and so on. However, real integration of memristors and CMOS circuits is very rarely available to most engineers and scholars who want to be involved in designing various kinds of CMOS circuits using memristors. To help those engineers and scholars who cannot access memristor fabrication technology but want to design memristor circuits, a CMOS emulator circuit that can reproduce the physical hysteresis loop of memristor's voltage-current relationship is needed.

## Methods

Before we develop a CMOS emulator circuit for memristor, memristive behavior should be explained first. The following simple equation (Equation 1) can describe the memristor's current-voltage relationship [1, 2]:

Here *v*(*t*) and *i*(*t*) represent the voltage and current of memristor, respectively. *R*_{
X
}(*t*) is the memristance that changes with respect to time. *R*_{SET} and *R*_{RESET} are SET and RESET resistance, respectively. *w*(*t*) is the effective width of the memristor. *D* is the total drift length of *w*(*t*). *q*(*t*) is an accumulated charge flow through the memristor. *Q*_{CRIT} means an amount of critical charge to RESET-to-SET transition. When *q*(*t*) becomes equal to Q_{CRIT}, *R*_{
X
}(*t*) is changed to *R*_{SET} from *R*_{RESET}. Here *μ*_{
v
} is the mobility of dopant in Equation 1 [1, 2].

To describe the memristive behavior that follows the relationship of current and voltage in Equation 1, a few emulator circuits have already been proposed [3–5]. Pershin and Ventra proposed an emulator circuit that is composed of an analog-to-digital converter and micro-controller that are implemented by discrete off-chip devices. Thus, they can be considered too much complicated and too large to be integrated in a single chip [3]. Jung et al. proposed an emulator circuit that is based on CMOS technology [4], where a memristor that should change its resistance in response to the applied current and voltage is implemented by an array of resistors. In the emulator circuit with resistor array, the analog-to-digital converter and the decoder circuit select a proper resistor among many resistors that are placed in the resistor array according to the applied voltage or current [4]. One problem in the emulator circuit [4] is that the voltage-current relationship seems sawtooth. This is because the resolution of memristance change is decided by the resolution of the analog-to-digital converter, as you see in [4]. If we have 4-bit analog-to-digital converter in the emulator circuit, it means that only 16 values of memristance are available. As a result, when we apply a voltage that is a sinusoidal function to the memristor, we can know that its current is increased or decreased like sawtooth. To improve the resolution of memristance change, the resolution of the analog-to-digital converter should be increased too. If the resolution of the analog-to-digital converter is improved from 4 to 5 bit, the voltage-current relationship of the emulator circuit with 5 bit seems to be much finer than the emulator circuit with a 4-bit analog-to-digital converter, as shown in [4]. To improve the resolution twice, however, the number of resistors in the resistor array should be double too. It can cause a large area overhead in realizing this emulator circuit in a single chip. Especially, in implementing memristor array with this emulator circuit, this large area overhead of each memristor emulator cell can be a serious problem because each cell in the memristor array should be realized by this large-area single memristor emulator.

To mitigate the large area overhead of the previous emulator circuit, we propose a new emulator circuit of memristors that is more compact and simpler than the previous emulator circuits [6]. The new emulator circuit does not use a resistor array, an analog-to-digital converter, and so on that usually occupy very large area. Instead of using the complicated circuit blocks that were mentioned just earlier, the new circuit can change its memristance value by a simple voltage-controlled resistor that can be realized by a single n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) device.

### Newly proposed emulator circuit for describing memristive behavior

A schematic of the proposed emulator circuit for describing memristive behavior is shown in Figure 1. The CMOS circuit for emulating memristive behavior is composed of transmission gates, comparators, current mirrors, voltage-controlled resistor, etc. as shown in Figure 1. *V*_{IN} is an input voltage source and *V*_{IN+} and *V*_{IN-}represent the anode and cathode of the input voltage source, respectively. In Figure 1, *V*_{IN+} is connected to TG_{1} and TG_{2} that are controlled by T_{B} and T, respectively. Similarly, *V*_{IN-} is connected to TG_{3} and TG_{4} that are controlled by T and T_{B}, respectively. When *V*_{IN+} is greater than *V*_{IN-}, T becomes high and T_{B} becomes low, by the comparator G_{1}. On the contrary, when *V*_{IN+} is smaller than V_{IN-}, T becomes low and T_{B} becomes high. Thus, we can know that *V*_{IN+} is connected to *V*_{A} through TG_{2} when *V*_{IN+} is larger than V_{IN-}. At the same moment, *V*_{IN-} is connected to the ground potential (GND) by TG_{3}. When *V*_{IN-} is larger than *V*_{IN+}, *V*_{IN-} is connected to *V*_{A} through TG_{4}, and *V*_{IN+} is biased by GND through TG_{1}. One thing to note here is that we can deliver the input voltage *V*_{IN} to *V*_{A} without any sacrificial voltage loss, using the transmission gate.

The *V*_{IN} delivering block that is composed of four transmission gates, TG_{1}, TG_{2}, TG_{3}, and TG_{4}, can deliver *V*_{IN+} and *V*_{IN-} that are plus and minus polarity of *V*_{IN}, respectively, to *V*_{A} that has only plus polarity, not minus. The delivered voltage *V*_{A} is copied exactly to *V*_{B} by the negative feedback circuit that is composed of the OP amp, G_{2}, M_{3}, and M_{4}. Using this circuit block, *V*_{B} can be the same as *V*_{A} by the feedback amplifier with unity gain. *V*_{B} is connected to the voltage-controlled resistor M_{2} that is controlled by *V*_{C}. One more thing to note here is that *V*_{C} controls both voltage-controlled resistors M_{1} and M_{2} that are electrically isolated from each other. By doing so, we can separate the memristor's current from the programming current to change the state variable that is stored at the capacitor C_{1}. If the memristor's current is not separated from the programming current, the state variable that decides memristance value can be maintained only at the moment when the programming voltage or current is applied to the memristor. If so, the emulator circuit cannot keep its programmed state variable when the applied voltage or current is removed.

*V*_{C} that controls two voltage-controlled resistors M_{1} and M_{2} acts as a state variable in the emulator circuit that is calculated by an amount of stored charge at *C*_{1}. When *V*_{IN+} is greater than *V*_{IN-}, TG_{7} is on and both TG_{5} and TG_{6} are off. At this time, the current mirror that is composed of M_{5} and M_{6} delivers the programming current to *C*_{1} to increase an amount of stored charge; thereby the state variable becomes larger. On the other hand, when *V*_{IN-} is greater than *V*_{IN+}, TG_{7} is off and both TG_{5} and TG_{6} are on. By doing so, we can decrease the amount of charge that is stored at the state variable capacitor*C*_{1}. The discharging current path is composed of M_{7}, M_{8}, M_{9}, and M_{10} in Figure 1. Here *V*_{BN} and *V*_{BP} are the biasing voltages for NMOSFETs and PMOSFETs, respectively. *V*_{BN} and *V*_{BP} are made from the biasing circuit that is shown in Figure 1. D_{1}, D_{2}, and D_{3} are the diodes that are used in the proposed emulator circuit to limit the minimum value of *V*_{C}. This minimum value of *V*_{C} is needed to avoid the dead zone which may be caused by the sub-threshold region of the voltage-controlled resistors M_{1} and M_{2}. *V*_{D} means the diode voltage of D_{1}, D_{2}, and D_{3}. *V*_{DD} is the power supply voltage of the CMOS emulator circuit in Figure 1.

One more thing to consider here is that the nonlinearity of memristive behaviors can be found when the effective width of memristor, *w*(*t*), in Equation 1 becomes much closer to the boundary constraints [1, 7]. This nonlinearity near the boundary values of *w*(*t*) was introduced in the HP model [1] and mathematically modeled by Corinto and Ascoli [7] to describe various nonlinear behaviors of memristors. In terms of implementation, the diode bridge circuit with LCR filter was proposed to reproduce memristive nature with nonlinearity by using a very simple electronic circuit [8]. In this paper, the window function that is used to define two boundary values of the state variable in the HP model [1] is realized in the CMOS emulator circuit that is shown in Figure 1. The emulator circuit in Figure 1 has two boundary values of the state variable that is defined by *V*_{C}. Here we can know that the maximum value of *V*_{C} cannot exceed *V*_{DD}. And also, *V*_{C} cannot be lower than *V*_{DD}-3*V*_{D}. Thus, the state variable of *V*_{C} in Figure 1 can exist only between *V*_{DD} and *V*_{DD}-3*V*_{D}, not being higher than *V*_{DD} and lower than *V*_{DD}-3*V*_{D}, respectively.

## Results and discussion

Figure 2a shows the applied input voltage, *V*_{IN}, to the proposed circuit for emulation of memristive behavior. The voltage waveform is sinusoidal and its frequency and magnitude are 10 kHz and 1.8 V, respectively. The memristor's current *I*_{IN} that is emulated by the proposed circuit in Figure 1 is shown in Figure 2b. As the sinusoidal voltage is applied to the emulator circuit in Figure 1, *I*_{IN} changes with respect to time according to the state variable that is represented by *V*_{C}, the amount of stored charge at C_{1}. When *V*_{C} has the lowest value, it means that the state variable is in RESET state, where the emulator circuit acts like a memristor with RESET resistance. After the half cycle of sinusoidal function, *V*_{C} is charged more and more; thereby *V*_{C} can reach the highest value. With the highest value of V_{C}, the state variable can be in SET state, where the emulator circuit can be considered a SET resistance. Figure 2c shows the voltage waveform of *V*_{C} with respect to time. At the starting point of sinusoidal function of *V*_{IN}, *V*_{C} is 1.2 V that is decided by D_{1} in Figure 1. After the half cycle of sinusoidal function, *V*_{C} reaches 2.8 V. When one cycle of sinusoidal function is completed, the *V*_{C} value returns to the value at the starting point of sinusoidal function. Figure 2d shows a typical pinched hysteresis loop of a memristor's voltage and current which are emulated by the proposed circuit in Figure 1. In the simulation, *V*_{DD} is 3.3 V and the frequency of sinusoidal function is 10 kHz.

Figure 2e, f, g, h shows the simulation results of the proposed emulator circuit with four times higher frequency of 40 kHz than that of Figure 2a, b, c, d, *V*_{IN}, *I*_{IN}, *V*_{C}, and the pinched hysteresis loop, respectively, with 10 kHz. A sinusoidal voltage with 40 kHz that is applied to the emulator circuit is shown in Figure 2e. Here the first three peaks are for increasing *V*_{C} in Figure 1; thereby, the emulator circuit changes from RESET to SET. The next three peaks are for decreasing the state variable; thus, the emulator circuit can return to RESET. *I*_{IN} and *V*_{C} with the sinusoidal function that is indicated in Figure 2e are shown in Figure 2f, g, respectively. Figure 2h shows the voltage-current relationship of the emulator circuit. In Figure 2h we can see three voltage-current loops at the right and another three voltage-current loops at the left which correspond to the three high peaks and three low peaks in Figure 2e, respectively.

Figure 3a shows SET pulses with different amplitude values. Here the amplitude values are increasing monotonically from 0.5 to 3 V. Each SET pulse is followed by a RESET pulse with the fixed amplitude as high as 3 V that is shown in Figure 3b. The state variable that is changed by SET and RESET pulses are shown in Figure 3c. Here *V*_{C} represents the amount of stored charge at C_{1} that controls the voltage-controlled resistor in Figure 1 that acts as memristor. Figure 4a shows the read and write circuits for the proposed emulator circuit of memristors [9, 10]. The read circuit is simply composed of a current mirror and comparator. The comparator G_{1} compares the sensing voltage *V*_{SEN} with the reference voltage *V*_{REF}. The sensing voltage *V*_{SEN} can change according to the programmed memristance value of the emulator circuit. If the state variable is closer to RESET, the sensing voltage *V*_{SEN} becomes larger due to a large value of memristance. On the contrary, the state variable is in SET, and *V*_{SEN} is smaller than *V*_{REF}. Here *D*_{OUT} is the output voltage of the read circuit. G_{2} is the inverter for RD that is the 'read’ command signal. TG_{1} and TG_{2} are the transmission gates for the read operation. When RD is high, TG_{1} and TG_{2} are on. On the contrary, TG_{3} and TG_{4} are on for the 'write’ operation that is activated by the write command signal WR. The input data *D*_{IN} drives the inverter G_{3}. And G_{3} drives the next inverter G_{4}. The anode and cathode of the proposed emulator circuit are driven by the two inverters, G_{3} and G_{4}, respectively. Figure 4b shows the voltage waveforms of *D*_{IN}, WR, RD, and *D*_{OUT}.

Figure 5 compares the layout area of the previous emulator circuit [4] and the proposed emulator circuit. Because the resistor array is not used in the proposed circuit and the analog-to-digital converter and decoder are eliminated in this paper, the layout area of the previous emulator circuit is estimated to be 32 times larger than the emulator circuit proposed in this paper. The design rule used in this layout is MagnaChip 0.35-μm technology.

## Conclusions

In this paper, a CMOS circuit that could emulate memristive behavior was proposed. The proposed emulator circuit could mimic the pinched hysteresis loops of a memristor's current-voltage relationship without using a resistor array and complicated circuit blocks that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit could mimic memristive behavior using simple voltage-controlled resistors, where the resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the emulator circuit proposed in this paper was estimated to be 32 times smaller than the previous emulator circuit.

## Authors’ information

SHS and JMC are M.S. students who are studying at the School of Electrical Engineering, Kookmin University, Seoul, Korea. SC is a professor at the Division of Electronics and Information Engineering, Chonbuk National University, Jeonju, Korea. KSM is a professor at the School of Electrical Engineering, Kookmin University, Seoul, Korea.

## References

- 1.
Strukov DB, Snider GS, Stewart DR, Williams RS: The missing memristor found.

*Nature*2008, 453: 80–83. 10.1038/nature06932 - 2.
Jo KH, Jung CM, Min KS, Kang SM: Memristor models and circuits for controlling Process-VDD-Temperature variations.

*IEEE Trans Nanotechnol*2010, 9(6):675–678. - 3.
Pershin YV, Ventra MD: Practical approach to programmable analog circuits with memristors.

*IEEE Trans Circuits Syst-I*2010, 57(8):1857–1864. - 4.
Jung CM, Jo KH, Min KS: SPICE macromodel and CMOS emulator for memristors.

*J Nanosci Nanotechnol*2012, 12(2):1487–1491. 10.1166/jnn.2012.4707 - 5.
Kim H, Sah MP, Yang C, Cho S: Memristor emulator for memristor circuit applications.

*IEEE Trans Circuits and Syst-I*2012, 59(10):2422–2431. - 6.
Choi JM, Shin SH, Cho SI, Min KS: CMOS circuit with small area and low complexity for emulating memristive behavior. In

*Collaborative Conference on 3D & Materials Research (CC3DMR)*. Jeju in Korea: ; 2013. - 7.
Corinto F, Ascoli A: A boundary condition-based approach to the modeling of memristor nano-structures.

*IEEE Trans Circuits and Syst-I*2012, 59(11):2713–2726. - 8.
Corinto F, Ascoli A: Memristive diode bridge with LCR filter.

*Electronics Letters*2012, 48(14):824–825. 10.1049/el.2012.1480 - 9.
Lee KJ, Cho BK, Cho WY, Kang S, Choi BG, Oh HR, Lee CS, Kim HJ, Park JM, Wang Q, Park MH, Ro YH, Choi JY, Kim KS, Kim YR, Shin IC, Lim KW, Cho HK, Choi CH, Chung WR, Kim DE, Yoon YJ, Yu KS, Jeong GT, Jeong HS, Kwak CK, Kim CH: A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput.

*IEEE J Solid-State Circuits*2008, 43(1):150–161. - 10.
Qureshi MS, Pickett M, Miao F, Strachan JP: CMOS interface circuits for reading and writing memristor crossbar array. In

*IEEE International Symposium on Circuits and Systems (ISCAS): 15–18 May 2011; Rio de Janeiro*. Piscataway: IEEE; 2011:2954–2957.

## Acknowledgements

This work was financially supported by the SRC/ERC program (R11-2005-048-00000-0), the Basic Science Research Program (2010–0023469), the Global Research Network Program (NRF-2011-220-D00089), the Nano-Material Technology Development Program (2011–0030228), and NRF-2013K1A3A1A25038533 through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning, and the Industrial Strategic Technology Development Program funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (10039239). The CAD tools were supported by the IC Design Education Center (IDEC), Korea.

A part of this work was presented at the Collaborative Conference on 3D & Materials Research (CC3DMR), Jeju, Korea, in June 2013.

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### Competing interests

The authors declare that they have no competing interests.

### Authors’ contributions

All authors have contributed to the submitted manuscript of the present work. KSM defined the research topic. SHS and JMC did the simulation and layout. SC provided critical comments on the draft manuscript. KSM wrote the paper. All authors read and approved the final manuscript.

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Shin, S., Choi, J., Cho, S. *et al.* Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.
*Nanoscale Res Lett* **8, **454 (2013) doi:10.1186/1556-276X-8-454

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- Emulator circuit
- CMOS emulator circuit
- Memristors
- Memristive behavior
- Nanoscale memristor memory
- CMOS/nanoscale memristor co-design

- 85.40.-e
- 85.35.-p