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Figure 2 | Nanoscale Research Letters

Figure 2

From: Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

Figure 2

Simulated voltage waveforms. The simulated voltage waveforms of (a) VIN, (b) IIN, (c) VC, and (d) the pinched hysteresis loop of the voltage-current relationship of the proposed emulator circuit when the sinusoidal frequency is 10 kHz. The simulated voltage waveforms of (e) VIN, (f) IIN, (g) VC, and (h) the pinched hysteresis loop of the voltage-current relationship of the proposed emulator circuit when the sinusoidal frequency is 40 kHz.

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