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Figure 4 | Nanoscale Research Letters

Figure 4

From: Enhanced resistive switching memory characteristics and mechanism using a Ti nanolayer at the W/TaO x interface

Figure 4

Cumulative probabilities of leakage currents and LRS/HRS and switching I - V curves of S1 and S2. (a) Cumulative probability of leakage currents for S1 and S2 devices with typical via size of 0.8 μm. Inset: leakage current vs. voltage characteristics. Switching I-V curves of (b) S2 and (c) S1 devices. The S2 device shows instability after a few cycles, while 10,000 consecutive switching cycles are observed for the S1 device. (d) Cumulative probability of LRS and HRS under Vread of ±1 V for the S1 devices.

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