Figure 2From: Dielectric properties of porous silicon for use as a substrate for the on-chip integration of millimeter-wave devices in the frequency range 140 to 210 GHzSchematic representation of local porous Si layer on Si wafer and geometry of CPW TLine. (a) Schematic representation of the locally formed porous Si layer on the Si wafer, on which the CPW TLine is integrated. (b) Topology of the CPW TLine with respective dimensions.Back to article page