- Nano Express
- Open Access
The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics
© Wong et al.; licensee Springer. 2014
- Received: 6 July 2014
- Accepted: 15 August 2014
- Published: 5 September 2014
When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La2O3/Si) MOS structure. We found that both W/La2O3 and La2O3/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes.
- Lanthanum oxide
- Si/high-k interface
- Metal gate/high-k interface
In the deca-nanometer complementary metal-oxide-semiconductor (CMOS) devices, the thickness of the gate dielectric film should be scaled down to the subnanometer equivalent oxide thickness (EOT) range in order to have proper control of the channel current under a reasonable gate bias[1–3]. This ultimate dielectric thickness requirement imposes a number of challenges on both the fabrication process and the device characteristic optimization. Interface properties and their thermal instabilities turn out to be the major challenging issues. Transition metal (TM)- or rare earth metal (RE)-based high-k dielectrics are extrinsic materials to the substrate silicon; they can react with silicon at some elevated temperatures[4–8], and the chemical reactions at the high-k/silicon interface cause most of the performance degradation issues. Conventional MOS layout for large-scale integration is in the planar structure, and the channel mobility of the transistors is predominately governed by the dielectric/silicon interface. Improvement of the SiO2/Si interface property had been one of the major concerns since the invention of the MOS transistor regardless of the fact that the SiO2/Si interface is already almost perfect as it is grown thermally in a self-organizing way from the intrinsic material[9–11], whereas the quality of the high-k metal/Si interface was found to be much poor. It was found that there exists a relative low-k transition layer between the TM/RE metal oxide and substrate silicon[12, 13]. This low-k layer may be of several angstroms to a nanometer thick and may become the major portion of the subnanometer EOT dielectric film. This transition layer, which cannot be scaled down for thinner high-k films, has become the major challenging issue for the subnanometer EOT thin film[1, 2]. The metal gate/high-k interface where a low-k transition layer may exist will also affect the resulting EOT; unfortunately, this issue was seldom studied. In this work, we took the tungsten/lanthanum oxide/Si (W/La2O3/Si) structure as an example to have a detailed study on the bonding structures together with thermal annealing effects on the W/La2O3 interface and La2O3/Si interface by employing combined angle-resolved X-ray photoelectron spectroscopy (ARXPS) and film thinning with in situ sputtering using an XPS source.
The tungsten/La2O3 gate stack was deposited on the n-type Si (100). A La2O3 film of about 5 nm thick was prepared by electron beam evaporation in an ultra-high vacuum chamber with a pressure of about 10−7 Pa. A tungsten gate electrode of about 3 nm thick was then deposited in situ using magnetron sputtering to avoid any moisture absorption and contamination. Some samples were further thermally annealed at 600°C for 30 min in a rapid thermal annealing furnace. The chemical compositions as well as the bonding structures of the as-prepared W/La2O3/Si stack at different depths were investigated in detail by using a Physical Electronics PHI 5802 spectrometer (Physical Electronics, Inc., Chanhassen, MN, USA) with monochromatic Al Kα radiation with an energy of 1,486.6 eV. To study the bonding structure on both W/La2O3 and La2O3/Si interfaces, both depth profiling by argon sputtering and angle-resolved techniques were used.
High-k/metal gate interface
It is further noted that the TEM picture also shows a rough interface between La2O3 and W. The rough interface should be due to the oxidation of tungsten and the reaction between La2O3 and tungsten at the interface. Although in real device applications, the W/La2O3 will not undergo such high-temperature annealing, the interface reaction should still exist in a certain extent as a similar phenomenon was also found in the sample which had undergone post-metallization annealing only.
Thermal budget and process sequences
In future technology nodes, the gate dielectric thickness of the CMOS devices will be scaled down to the subnanometer range. Lanthanum-based dielectric films have been considered to be suitable candidates for this application. This work presented a detailed study on the interface bonding structures of the W/La2O3/Si stack. We found that thermal annealing can lead to W oxidation and formation of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers will become the critical constraint for the smallest achievable EOT, and they would also cause a number of instability issues and induce device performance degradation. These issues can be minimized by lowering the thermal budgets and re-shuttling the process sequences.
This work is supported by the National Natural Science Foundation of China under grant no. 61376111.
- Wong H, Zhang J: Challenges of next generation ultrathin gate dielectrics. In Proc IEEE Int Symp Next Generation Electronics; Taoyuan. Piscataway: IEEE Press; 2014.Google Scholar
- Wong H: Nano-CMOS Gate Dielectric Engineering. Boca Raton: CRC Press; 2012.Google Scholar
- Wong H, Iwai H: On the scaling issues and high-k replacement of ultrathin gate dielectrics for nanoscale MOS transistors. Microelectron Engineer 2006, 83: 1867–1904. 10.1016/j.mee.2006.01.271View ArticleGoogle Scholar
- Lichtenwalner DJ, Jur JS, Kingon AI, Agustin MP, Yang Y, Stemmer S, Goncharova LV, Gustafsson T, Garfunkel E: Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction. J Appl Phys 2005, 98: 024314. 10.1063/1.1988967View ArticleGoogle Scholar
- Yamada H, Shimizu T, Suzuki E: Interface reaction of a silicon substrate and lanthanum oxide films deposited by metalorganic chemical vapor deposition. Jpn J App Phys 2002, 41: L368–370. 10.1143/JJAP.41.L368View ArticleGoogle Scholar
- Wong H, Ng KL, Zhan N, Poon MC, Kok CW: Interface bonding structure of hafnium oxide prepared by direct sputtering of hafnium in oxygen. J Vac Sci Technol B 2004, 22: 1094–1100. 10.1116/1.1740764View ArticleGoogle Scholar
- Lucovsky G: Bond strain and defects at Si-SiO2 and dielectric interfaces in high-k gate stacks. In Frontiers in Electronics. Edited by: Iwai H, Nishi Y, Shur MS, Wong H. Singapore: World Scientific; 2006:241–262.View ArticleGoogle Scholar
- Lucovsky G: Electronic structure of transition metal/rare earth alternative high-k gate dielectrics: interfacial band alignments and intrinsic defects. Microeletron Reliab 2003, 43: 1417–1426. 10.1016/S0026-2714(03)00253-1View ArticleGoogle Scholar
- Lucovsky G, Phillips JC: Microscopic bonding macroscopic strain relaxations at Si-SiO2 interfaces. Appl Phys A 2004, 78: 453–459.View ArticleGoogle Scholar
- Fitch JT, Bjorkman CH, Lucovsky G, Pollak FH, Yim X: Intrinsic stress and stress gradients at the SiO2/Si interface in structures prepared by thermal oxidation of Si and subjected to rapid thermal annealing. J Vac Sci Technol B 1989, 7: 775–781.View ArticleGoogle Scholar
- Lucovsky G, Yang H, Niimi H, Keister JW, Rowe JE, Thorpe MF, Phillips JC: Intrinsic limitations on device performance and reliability from bond-constraint induced transition regions at interfaces of stacked dielectrics. J Vac Sci Technol B 2000, 18: 1742–1748. 10.1116/1.591464View ArticleGoogle Scholar
- Wong H, Iwai H: Modeling and characterization of direct tunneling current in dual-layer ultrathin gate dielectric films. J Vac Sci Technol B 2006, 24: 1785–1793. 10.1116/1.2213268View ArticleGoogle Scholar
- Wong H, Iwai H, Kakushima K, Yang BL, Chu PK: XPS study of the bonding properties of lanthanum oxide/silicon interface with a trace amount of nitrogen incorporation. J Electrochem Soc 2010, 157: G49-G52. 10.1149/1.3268128View ArticleGoogle Scholar
- Kawanago T: A study on high-k/metal gate stack MOSFETs with rare earth oxides. In Ph.D. Dissertation. Japan: Tokyo Institute of Technology; 2011.Google Scholar
- Wong H, Sen B, Yang BL, Huang AP, Chu PK: Effects and mechanisms of nitrogen incorporation in hafnium oxide by plasma immersion implantation. J Vac Sci Technol B 2007, 25: 1853–1858. 10.1116/1.2799969View ArticleGoogle Scholar
- Wong H, Yang BL, Kakushima K, Ahmet P, Iwai H: Effects of aluminum doping on lanthanum oxide gate dielectric films. Vacuum 2012, 86: 929–932. 10.1016/j.vacuum.2011.06.023View ArticleGoogle Scholar
- Sen B, Wong H, Molina J, Iwai H, Ng JA, Kakushima K, Sarkar CK: Trapping characteristics of lanthanum oxide gate dielectric film explored from temperature dependent current-voltage and capacitance-voltage measurements. Solid State Electron 2007, 51: 475–480. 10.1016/j.sse.2007.01.032View ArticleGoogle Scholar
- Perevalov TV, Gritsenko VA, Erenburg SB, Badalyan AM, Wong H, Kim CW: Atomic and electronic structure of amorphous and crystalline hafnium oxide: x-ray photoelectron spectroscopy and density functional calculations. J Appl Phys 2007, 101: 053704. 10.1063/1.2464184View ArticleGoogle Scholar
- Sakamoto K, Huda M, Ishii K: Self-aligned planar double-gate field-effect transistors fabricated by a source/drain first process. Jpn J Appl Phys 2005, 44: L147. 10.1143/JJAP.44.L147View ArticleGoogle Scholar
This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly credited.