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Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding
Nanoscale Research Letters volume 9, Article number: 541 (2014)
This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach.
Conventional quartz resonator components are packaged in metal lid with ceramic-based interposer enclosures. In order to keep frequency components from moisture or other contamination and mechanical attack, quartz resonator requires specialized packaging with the protective cap over the quartz resonator blank [1, 2]. With these technologies of metal lid and ceramic substrate, current quartz resonator can be fabricated in a size of 1.6 × 1.2 mm. However, challenges and issues of current manufacturing of ceramic-based quartz resonator package, including high-cost packaging material of metal lid, one chip sealing bonding, and scaling limit of ceramic substrate, make the shrinkage of quartz resonator packages difficult. For this reason, to develop a new packaging method with quartz resonator is necessary to solve the abovementioned difficulties and achieve a high performance, small form factor, and low manufacturing cost [3, 4].
In recent years, with the development of wireless communication, the small form factor, low cost, and high-performance microelectronic products become significant due to the need of market. Multi-chips integration is the trend of the present semiconductor and package industries due to advantages mentioned above. Among the multi-chips integration techniques, three-dimensional (3D) integration is one of the most promising approaches in microelectronic integration and package techniques [5–11]. 3D integration technologies achieve heterogeneous integration and offer a smaller area solution for electronic products by the Cu through-silicon via (TSV) interconnection and vertical stacking. Several 3D integration schemes have been proposed in worldwide institutes to establish 3D integration platforms [12–17]. The 3D scheme combined with sealing bonding techniques by using sealing wafer level packaging of micro electro mechanical system (MEMS) component is successfully achieved, such as SAW RF Filter, silicon MEMS oscillators, and image sensor devices [18–22].
In this research, an innovated assembling design of quartz resonator package using TSV interposer is proposed not only to replace ceramic substrate but also to solve difficulty of scaling down by using general semiconductor techniques. In addition, corresponding silicon-based sealing cap structures are also demonstrated to replace traditional high cost metal lid. This silicon-based quartz resonator package is achieved by the Cu TSV interconnection, wafer thinning process, and sealing bonding techniques. With the combination of silicon-based design and quartz resonator, the advanced techniques of wafer level package to replace one chip sealing packaging are feasible and can offer low-cost packaging solution. The complete study of structure design, component characterization, and reliability evaluation for the innovated assembling design by using 3D integration scheme is presented to offer one potential solution for the next generation of quartz resonator components.Figure 1a shows the traditional quartz resonator component packaged in metal lid with ceramic-based interposer enclosures. In this paper, we demonstrate a novel silicon-based packaging approach by using 3D integration with general semiconductor techniques. This designed package is similar to conventional quartz resonator package but not metal lid with ceramic-based interposer assembling fabrication. Two novel silicon-based packages with quartz resonator using the concept of 3D integration are displayed in Figure 1b,c. The wafer level TSV interposer is implemented in both designs to replace traditional chip level ceramic-based interposer. The main difference of two silicon-based packages is about the silicon-based cap designs. Figure 1b is sealed with silicon cap through Cu/Sn eutectic bonding, and other is directly sealed by SU-8 polymer ring with polymer formed cavity in Figure 1c.
TSV interposer design
Simulations about mechanical structure and electrical characteristics are performed to evaluate the design of TSV interposer. For the electrical characteristics, the total capacitances including self-capacitance and stray coupling capacitances are considered to evaluate the capacitance properties of TSV interposer by using Ansoft Q3D Extractor software (Ansys, Inc., Cecil Township, Pennsylvania, USA). The size of TSV interposer is 1.2 × 1.0 mm2 with different conditions of designed structural substrate, such as Cu TSV diameter, TSV pitch, and thickness of substrate are considered. Figure 2 shows the results of this structure using different dimensions of each component, where TSV diameters are 25, 50, and 100 μm under the fixed 100-μm interposer thickness and 300-μm TSV pitch; TSV pitches are 300, 400, and 500 μm under the fixed 25-μm TSV diameter and 300-μm TSV pitch; thicknesses of substrate are 100, 200, and 300 μm under the fixed 25-μm TSV diameter and 100-μm interposer thickness. The results show that interposer thickness is the main factor of the total capacitance in the whole TSV interposer design. However, the designs of TSV diameter and pitch have a tiny impact on total capacitance, compared to interposer thickness. Therefore, the capacitance of designed TSV interposer can be adjusted by changing the interposer thickness.
According to the above simulation results, the influence of total capacitance of Ag pad design is also evaluated under a different interposer size in a 1.2 × 1.0 mm2 substrate with 250-μm thickness and 100-μm diameter Cu TSVs. The Ag pad not only connects with Cu TSV but also provides the area to mount the quartz resonator with Ag conductive glue. Figure 3 shows the capacitance simulation results for Ag pad on TSV interposer based on altering pad area and thickness. Changing the Ag pad thickness has unapparent influence on total capacitance under the fixed 250-μm2 Ag pad area. However, Ag bump area has an obvious effect on total capacitance with fixed 1-μm Ag pad thickness. With capacitance simulation results, the whole capacitance of TSV interposer is adjustable in the manufacturing process.
On the other hand, the thermal stress simulation of designed TSV interposer is implemented by COMSOL Multiphysics software (COMSOL, Inc., Burlington, MA, USA) to evaluate thermal stress issues. In this case, thermal stress simulation contains thermal module and mechanical stress module simultaneously. The effect of a different interposer size in a 1.2 × 1.0 mm2 substrate with 250-μm thickness and 100-μm diameter Cu TSVs is evaluated by the thermal stress distribution at temperature condition from room temperature to 700 K. Because of the thermal budget of quartz resonator integration, the maximum temperature value is set up for 700 K. From the thermal stress simulation results in Figure 4a, it is clear that the main thermal stress occurs around Cu TSV profile of TSV interposer. In addition, with the quantification of thermal stress, the interface of Cu/SiO2 has the maximum thermal stress due to the coefficient of thermal expansion (CTE) mismatch in Figure 4b. In this study, although there is thermal stress around the sidewall of TSV, the value of maximum thermal stress is 1.559 GPa, which is still below yield strength of silicon for 7 GPa  (The yield strength of material can withstand without permanent deformation or fracture). For this reason, this interposer should be robust without cracking or deforming the TSV interposer under the thermal budget for 700 K. With the assistance of simulation results, the optimized TSV interposer can be achieved to integrate with quartz resonator.
Component with TSV interposer
After evaluating the designed interposer with simulation, the TSV interposer is demonstrated through the integration of Cu TSVs and wafer thinning process. The TSV interposer is fabricated with the design of 100-μm diameter and 250-μm depth Cu TSVs. To connect Cu TSVs, the redistribution metal layers are patterned on both the front-side for quartz resonator mount pad and on the backside for connection pad. Finally, the fabrication of TSV interposer is completed after patterning redistribution metal layers on both sides. The follow-up process is the heterogeneous integration between quartz resonator and TSV interposer. In order to integrate quartz resonator with designed interposer, the Ag conductive glue is applied on front-side Ag pad to attach quartz resonator, as shown in Figure 5. In order to ensure the quartz resonator fixed on front-side Ag pad of TSV interposer and avoid the collapsed Ag conductive glue occurring, a curing process is necessary.
Ag conductive glue is composed of Ag micro-ball with dense glue, which is not only for electrical connection between the quartz resonator and front-side Ag pad but also for providing the required space from silicon interposer for quartz resonator to operate mechanical vibration. In addition, the Ag conductive glue may release the thermal stress near front-side Ag pad surface and mechanical stress during quartz resonator vibration due to the flexible property. Therefore, this Ag conductive glue plays an important role in the heterogeneous integration between quartz resonator and TSV interposer. Overall, this novel design of quartz resonator with TSV interposer is fabricated successfully in wafer level process, and this scheme can provide the possibility to replace traditional one chip ceramic-based interposer.
Thinned Si-cap and Si-polymer cap processing
For replacing the traditional metal lid of quartz resonator package, two types of silicon-based cap structure are developed with the same size of 1.2 × 1.0 mm2 cap and 0.84 × 0.64 mm2 cavity inside in general semiconductor techniques. Type 1 uses thinned Si-cap, which requires a protective cavity on silicon substrate by using deep reactive-ion etching (DRIE) method with Cu/Sn sealing ring around. Type 2 uses thinned Si-polymer cap, which uses SU-8 polymer ring as cap structure, providing sealing purpose by bonding without extra process. Before the fabrication of two cap structures, the mechanical reliability of two cap structures is considered for bending condition through COMSOL Multiphysics software (COMSOL, Inc., Burlington, MA, USA), as shown in Figure 6. In the beginning, the testing cap is placed on the middle of the bending broad with the fixed force for 2,450 Nt on broad. For the study of thinned Si-cap bending stress, the thinned Si-cap structure is evaluated by reducing the cap thickness from 400 to 200 μm with cavity depth of 180 μm. The maximum bending stress of thinned Si-cap always occurs at the four corners of inner cavity and decreases with increasing substrate thickness. Since the maximum bending stress of this structure is 1.559 GPa, which is still below the yield strength of silicon for 7 GPa , this thinned Si-cap design should be robust for the mechanical point of view.
In addition, the thinned Si-polymer cap structure with substrate thickness of 100 μm and SU-8 sealing ring thickness of 100 ~ 250 μm is also evaluated with the same bending condition. Obviously, the maximum bending stress of thinned Si-polymer cap is much smaller than thinned Si-cap cases. The results show the maximum bending stress of thinned Si-polymer cap always occurs at thinned Si substrate corners, but not at the interfaces of silicon and SU-8 polymer. Due to less mechanical stress compared to thinned Si-cap, this thinned Si-polymer cap is also robust as thinned Si-cap type without cracking or deforming substrate. Therefore, this bending simulation can provide a guideline for cap structure design among the two types. With the bending simulation results, the suitable cap structure can be achieved by replacing the metal lid of traditional quartz resonator.According to the results of bending simulation, the two types of cap structure are developed in each manufacturing process. For thinned Si-cap integration, silicon wafers with the thickness of 525 μm are thinned to 300-μm thick substrate in the beginning. Before thinned Si-cap wafer etching process, the Cu/Sn seal ring with the thickness of 4/2 μm is deposited on thinned Si-cap bonding areas for the next hermetic bonding purpose. Subsequently, the DRIE tool is used to form a depth of 150-μm cavities in wafer level using photoresist as etching mask. On the other hand, the fabrication of thinned Si-polymer cap is implemented and patterned on the 120-μm depth cavity structure through lithography process, as shown in Figure 7.
Results and discussion
Thermal stress issues
Considering the thermal reliability of the integration of quartz resonator and this designed interposer, thermal process is implemented to inspect the quality of quartz resonator with TSV interposer. The thermal process is carried out with temperature condition from room temperature to 300°C for 24 h. Figure 8a,b shows the top view and cross-sectional scanning electron microscope (SEM) images of quartz resonator with TSV interposer after thermal reliability investigation. Without the deformations and cracks, the results indicate an excellent integrity for the integration of Cu TSV, Ag conductive glue and quartz resonator. In addition, the interfaces of Cu TSV/SiO2/Si layers are investigated with and without thermal process, as shown in Figure 8c,d. There are still no cracks or voids between the interfaces of TSV/SiO2/Si layers which indicate good quality of Cu TSV fabrication and are consistent with the above simulation results. Therefore, this thermal reliability results confirm a reliable and stable integration between quartz resonator and TSV interposer with thermal process investigation.
Figure 9a shows the vector network analyzer with pi circuits for measurement of quartz resonator with TSV interposer. Since the vector network analyzer is used for conventional quartz resonator package, such as ceramic with metal lid type , it is used for investigating the electrical performances and frequency response of this novel integration of quartz resonator and TSV interposer. By using vector network analyzer, the equivalent circuit, Butterworth-Van Dyke, of silicon-based quartz resonator can be extracted. The frequency characteristics of two standard quartz resonators (26 and 37 MHz) integrated with TSV interposer are measured. Thus, Figure 9b can display the components of Butterworth-Van Dyke equivalent circuit, including C1, L1, R1, and C0, of two standard silicon-based quartz resonators.The frequency responses of each quartz resonator with TSV interposer are shown in Figure 9c. It is indicated that the specific oscillating frequency (approximately 26 and 37 MHz) can be outputted and employed to validate the feasibility in this research.
Bonding reliability and pull test
To study the further bonding reliability of two cap structures with the designed interposer, the thermal processes are implemented to examine the bonding interfaces of thinned Si-cap and thinned Si-polymer cap. The reliability tests of two type bonding interfaces are investigated in serial thermal process flow (annealing for 200°C, curing for 250°C, reflow for 260°C, and aging for 125°C) based on general quartz resonator thermal process. The two cap bonding interfaces are examined by the cross-sectional SEM images, as shown in Figure 10. It shows the excellent bonding integrity without voids or seams in two cap bonding interfaces for the follow-up thermal process. Based on the evidences of SEM profile, these two cap structures both show the robust bonded layer, which may be suitable cap sealing technologies with quartz blank for next generation of quartz resonator device.
In order to understand the mechanical strength of two cap bonding structures, the bonded cap structures (thinned Si-cap and thinned Si-polymer cap) with different temperature conditions are executed and then examined through pull test, as illustrated in Table 1. The pull test tool is set up with 15 × 15 mm bonded cap structures. The results of Si-cap show an excellent mechanical strength without de-bonds in the range of 250°C ~ 280°C but a failure at the location of original bonding interface after bonding 320°C and preliminary tests. It indicates that the Cu/Sn bonding structure remains intact under the bonding condition of 250°C ~ 280°C. On the other hand, the results of bonded thinned Si-polymer cap display the bonding interfaces which have acceptable enhancement under the bonding condition less than 250°C. However, when the bonding temperature is increased above the temperature of 300°C, the bonding mechanical strength decreases obviously. Due to the thermal budget limitation of quartz resonator limitation, the temperature of thermal/bonding process has to be as low as possible. These thinned Si-cap and thinned Si-polymer cap structures show the strong potential to replace the conventional metal lid. Furthermore, because of SU-8 polymer with lower temperature bonding condition, the thinned Si-polymer cap can achieve sealing process easily with a low temperature process, compared with traditional structures.
Based on the advantages of cost efficient, easy to scale down, and wafer level sealing process, the thinned Si-cap and thinned Si-polymer cap structures have potential to offer feasible approach for the future advanced quartz resonator package.
The optimum design, simulation, fabrication, and performances of wafer level packaging approach of quartz resonator based on TSV interposer with metal or polymer bonding are reported in this paper. This design is different from the conventional quartz resonator using ceramic-based package. This quartz resonator is designed with sealing bonding, wafer thinning, and Cu TSV interconnection. The silicon-based quartz resonator is able to meet the demands of small size and cost-effective technologies and also demonstrates the potential in advanced quartz resonator applications.
coefficient of thermal expansion
deep reactive ion etching
micro electro mechanical systems
scanning electron microscope
Abe T, Kishi H: Design and fabrication of a Gaussian-shaped AT-cut quartz crystal resonator. IEEE 22nd Micro Electro Mechanical Systems International Conference: 25–29 Jan 2009; Sorrento, Italy 2009, 908–911.
Beelen-Hendrikx C, Verguld M: Trends in electronic packaging and assembly for portable consumer products. In Proceedings of Electronics Packaging Technology Conference (EPTC) 2000. Eindhoven, Netherlands; 2000:24–32.
Matthys RJ: Crystal Oscillator Circuits. New York: John Wiley & Sons; 1983.
Nagaura Y, Yokomizo S: The machining and characteristics of an ultra-thin, plano-convex-type quartz oscillator. Proceedings of the 1998 IEEE Frequency Control Symposium: 27–29 May 1998; Pasadena 1998, 844–847.
Peng CT, Lin JC, Lin CT, Chiang KN: Performance and package effect of a novel piezoresistive pressure sensor fabricated by front-side etching technology. Sensors Actuators A Phys 2005, 119: 28–37. 10.1016/j.sna.2004.08.013
Topol A, Tulipe DCL, Shi L, Frank D, Bernstein K, Steen S, Kumar A, Singco G, Young A, Guarini K: Three-dimensional integrated circuits. IBM J Res Dev 2006, 50: 491–506.
Semiconductor Industry Association: International Technology Roadmap for Semiconductors. San Jose, CA; 2001.
Jourdain A, Buisson T, Phommahaxay A, Redolfi A, Thangaraju S, Travaly Y, Beyne E, Swinnen B: Integration of TSVs, wafer thinning and backside passivation on full 300 mm CMOS wafers for 3D applications. In Proc. of Electronic Components and Technology Conf.: 31 May 2011- 3 June 2011; Orlando. Orlando, USA; 2011:1122–1125.
Chen KN, Tan CS, Fan A, Reif R: Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing. Appl Phys Lett 2005, 86: 011903. 10.1063/1.1844609
Chen KN, Fan A, Tan CS: Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology. IEEE Electron Device Lett 2004, 25: 10–12. 10.1109/LED.2003.821591
Chen KN, Lee SH, Andry PS, Tsang CK, Topol AW, Lin YM, Lu JQ, Young AM, Ieong M, Haensch W: Structure, design and process control for Cu bonded interconnects in 3D integrated circuits. In Proc. IEDM.: 11–13 Dec 2006. San Francisco; 2006:367–370.
Zoschke K, Wolf J, Ehrmann O, Reichl H: Temporary wafer bonding for wafer thinning and backside processing - key technology for 3D system integration. Proceeding of 2nd IEEE Workshop on Low Temperature Bonding for 3D Integration. Tokyo, 19–20 2010, 331–354.
Matthias T, Kim B, Wimplinger M, Lindner P: Thin wafer processing and chip stacking for 3D integration. In Proc. Electronics System Integration Technology Conference: 13–16 Sept 2010. Berlin; 2010.
Liu F, Yu R, Young A, Doyle J, Wang X, Shi L, Chen KN, Li X, Dipaola D, Brown D: A 300-mm wafer-level three dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding. In Proc. IEDM: 15–17 Dec 2008. San Francisco; 2008:1–4.
Pozder S, Jain A, Chatterjee R, Huang Z, Jones RE, Acosta E, Marlin B, Hillmann G, Sobczak M, Kreindl G: 3D die-to-wafer Cu/Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding. In Interconnect Technology Conference: 1–4 June 2008. Burlingame; 2008:46–48.
Jürgensen N, Huynh QH, Engelmann G, Ngo H-D, Ehrmann O, Lang K-D, Uhlig A, Dretschkow T, Rohde D, Worm O, Jäger C: Copper filling of TSVs for interposer applications. In 2012 IEEE 14th Electronics Packaging Technology Conference: 5–7 Dec 2012. Singapore; 2012:809–813.
Zoschke K, Wolf J, Lopper C, Kuna I, Jürgensen N, Glaw V, Samulewicz K, Röder J, Wilke M, Wünsch O, Klein M, Suchodoletz MV, Oppermann H, Braun T, Ehrmann O: TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules. In 61st Electronic Components and Technology Conference: 31 May 2011- 3 June 2011. Orlando; 2011:836–843.
Lim J-H, Hwang J-S, Kwon J, Ham S-J, Kim W, Kim T, Jeung WK, Yang SJ, Choi SM, Park JH: An ultra small SAW RF Filter using wafer level packaging technology. In Proc. 2006 IEEE Ultrasonic Symposium: 2–6 Oct 2006. Vancouver; 2006:196–199.
Viswanadam G, Bieck F, Suthiwongsunthor N: Novel wafer level package technology studies for image sensor devices. In Electronics Packaging Technology Conference 2005: 7–9 Dec 2005; Singapore. Singapore; 2005:153–157.
Kim TH, Jeung WK, Yang SJ, Choi SM, Park SW, Kim HH, Ha J, Park MJ, Kao S, Hong JP, Yi S, Hwang JS, Lim JH, Kim WB: Miniaturization and optimization of RF SAW Filter using wafer level packaging technology. In Proc 57th Electronic Components and Technology Conference: 29 May 2007- 1 June 2007. Reno; 2007:574–579.
Hsu W-T, Pai M: The new heart beat of elctronics-silicon MEMS oscillators. In Proc 57th Electronic Temperature (°C) Components and Technology Conference: 29 May 2007- 1 June 2007. Reno; 2007:1895–1899.
Hsu WT: Reliability of silicon resonator oscillators. International Frequency Control Symposium and Exposition 2006 IEEE. Miami, FL: June 2006 389–392.
Petersen KE: Silicon as a mechanical material. In Proceeding of the IEEE. Fremont, CA; 1982. 70(5):420–457 70(5):420–457
This work is supported in part by the Ministry of Education in Taiwan under ATU Program and Ministry of Science and Technology through Grant No. MOST 102-2221-E-009-160 and MOST 103-2221-E-009-173-MY3. The authors acknowledge the facility assistance of using the fabrication facilities from National Chiao Tung University and TXC Corporation.
The authors declare that they have no competing interests.
J-YS wrote the manuscript and proceeded the research. J-YS and Y-CC integrated the quartz resonator with TSV interposer. C-HC, C-LL, and C-CC participated in the research concept. K-NC participated in the research concept, guided the research, and revised the manuscript. All authors read and approved the final manuscript.
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Shih, J., Chen, Y., Chiu, C. et al. Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding. Nanoscale Res Lett 9, 541 (2014). https://doi.org/10.1186/1556-276X-9-541
- Three-dimensional (3D) integration
- Through-silicon via (TSV)
- Wafer thinning
- Sealing bonding