Skip to main content
Account
Figure 5 | Nanoscale Research Letters

Figure 5

From: Coexistence of memory resistance and memory capacitance in TiO2 solid-state devices

Figure 5

Schematic, circuit, and results of the proposed model. (a) Schematic view of our TiO2- based two-layer devices. (b) The equivalent circuit model with two parallel RC elements connected in series. (c) Threshold-based dynamics of the state variable x (normalised width of the TiO x layer). (d) Simulated resistive and capacitive switching trends which correlated with experimental results in FigureĀ 4.

Back to article page

Navigation