A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
© Yeh et al.; licensee Springer. 2014
Received: 27 June 2014
Accepted: 16 October 2014
Published: 6 November 2014
This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. In the future, this device will be applied to multi-layer Si ICs in fully functional systems on panels, active-matrix liquid-crystal displays, and three-dimensional (3D) stacked flash memory.
KeywordsSingle poly-Si Gate-all-around Junctionless Fin field-effect transistor One-time programming Nonvolatile memory Three-dimensional Flash memory
In this work, a JL channel[6–11] is introduced into the single poly-Si structure. The use of the JL channel enables the short channel effect (SCE) to be reduced and a simple implantation process to be used. The single poly-Si JL-FinFET NVM reduces the leakage current, according to Moore’s law, significantly reducing the development time and fabrication cost. JL NW devices with high doping concentrations in their channel and source/drain (S/D) regions have attracted much interest. The advantages of these devices over conventional inversion mode devices are (1) lack of need for an ultra-shallow S/D junction, which simplifies the fabrication process; (2) a low thermal budget, because of the elimination of the need for implant activation annealing after gate stack formation; and (3) concentration of the current of the JL device on the bulk of the semiconductor, which reduces the adverse effects of imperfect interfaces between the semiconductor and the insulator.
The channel is designed with a GAA structure to ensure that the gate can be effectively controlled[12, 13]. GAA devices have an on/off ratio of 107 and a subthreshold swing (SS) of 150 mV/decade, which can be easily obtained when the thickness of the JL channel is well controlled[14, 15].
The one-time programming (OTP) memory device can be programmed at high speed; it exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. Therefore, this work develops a high-performance single poly-Si GAA JL-FinFET NVM, which has high programming speed and excellent reliability.
In this work, a single poly-Si JL-FinFET NVM with an oxide/nitride layer is fabricated. Figure 1a schematically depicts the single poly-Si JL-FinFET NVM with ten NWs and the device has GAA-NWs. The gate electrodes of two TFTs are connected to form the floating gate (FG), while the source and drain of the larger TFT (T2) are connected to form the control gate.
The aforementioned devices were fabricated by initially growing a 400-nm-thick thermal oxide layer on 6-in. silicon wafers as substrates. A thin 50-nm-thick undoped amorphous-Si (a-Si) layer was then deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. The deposited a-Si layer was then solid-phase crystallized (SPC) at 600°C for 24 h in nitrogen ambient. A 2 × 1014 cm−2 dose of phosphorus was implanted and the device was then annealed to form the n-type active layer. The active device was patterned by electron beam (e-beam) direct writing and transferred by reactive ion etching (RIE). The device was dipped in hydrogen fluoride (HF) solution for 120 s to suspend the NWs in midair.
To enable the JL device to be controlled, the channel must be trimmed in the thickness direction. Therefore, the naked NWs can form by thermal oxidation which grew the 24-nm oxide layer and then dipped in HF for 100 s to remove the first sacrificial oxide layer. The dipped HF condition can keep the buried oxide sustain NWs (Figure 2c). Secondly, thermal oxidation is performed to produce a tunnel oxide layer with a thickness of 3 nm. Then, LPCVD is conducted to deposit a 7-nm-thick nitride layer as storage layer. The gate regions are formed by in situ doping with phosphorus ions to form the n-type poly gate. The channel of the device thus formed has a GAA structure.
On such devices, a 200-nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD. Next, the contact holes were defined and a 300-nm-thick Al-Si-Cu metallization was performed. Finally, the device was sintered at 400°C in nitrogen ambient for 30 min.
Results and discussion
Recently, the embedded NVM has been extensively applied to different systems. A device that can only be programmed once, which is called a ‘one-time programmable device’ , plays an important role in CMOS technology. OTP has always attracted much interest because of the ease of the process flow and its high performance, which reduce the cost of the process.
This work demonstrates the potential of the single poly-Si JL-FinFET GAA NVM for use in OTP operations and its easy embedding into logic circuits. The device can be programmed by FN tunneling but not easily erased, owing to the high dopant concentration. The GAA structure provides good control ability. The device exhibits excellent retention and the memory window can be maintained at 2 V after 108 s, with at least 95% of the original charge stored for more than 10 years. At 200°C, in a high-temperature retention test, the device exhibits better retention than at low temperature. Measurements demonstrate that the device has a lower fabrication cost and greater scalability than the conventional OTP memory. Therefore, the single poly-Si JL-FinFET GAA NVM is an effective embedded NVM for advanced logic technologies.
The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under contract no. MOST 103-2221-E-007 -114 -MY3. The National Nano Device Laboratories is greatly appreciated for its technical support.
- Yeh MS, Wu YC, Hung MF, Liu KC, Jhan YR, Chen LC, Chang CY: Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory. Nanoscale Res Lett 2013, 8: 331. 10.1186/1556-276X-8-331View ArticleGoogle Scholar
- Hung MF, Wu YC, Tsai TM, Chen JH, Jhan YR: Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory. Appl Phys Express 2012, 5: 121801. 10.1143/APEX.5.121801View ArticleGoogle Scholar
- Wu YC, Su PW, Chang CW, Hung MF: Novel twin poly-Si thin-film transistors EEPROM with trigate nanowire structure. IEEE Electron Device Lett 2008, 29: 1226.View ArticleGoogle Scholar
- Wu YC, Hung MF, Su PW: Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH3 plasma passivation. J Electrochem Soc 2011, 158: H578. 10.1149/1.3560576View ArticleGoogle Scholar
- Hung MF, Wu YC, Chang JJ, Chang-Liao KS: Twin thin-film transistor nonvolatile memory with an indium–gallium–zinc–oxide floating gate. Appl Phys Lett 2013, 34: 1.Google Scholar
- Li X, Han W, Wang H, Ma L, Zhang Y, Du Y, Yang F: Low-temperature electron mobility in heavily n-doped junctionless nanowire transistor. Appl Phys Lett 2013, 102: 223507. 10.1063/1.4809828View ArticleGoogle Scholar
- Rudenko T, Nazarov A, Ferain I, Das S, Yu R, Barraud S, Razavi P: Mobility enhancement effect in heavily doped junctionless nanowire silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 2012, 101: 213502. 10.1063/1.4767353View ArticleGoogle Scholar
- Sorée B, Magnus W, Vandenberghe W: Low-field mobility in ultrathin silicon nanowire junctionless transistors. Appl Phys Lett 2011, 99: 233509. 10.1063/1.3669509View ArticleGoogle Scholar
- Lee CW, Nazarov AN, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Doria RT, Colinge JP: Low subthreshold slope in junctionless multigate transistors. Appl Phys Lett 2010, 96: 102106. 10.1063/1.3358131View ArticleGoogle Scholar
- Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu RA, Nazarov AN, Doria RT: Reduced electric field in junctionless transistors. Appl Phys Lett 2010, 96: 073510. 10.1063/1.3299014View ArticleGoogle Scholar
- Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP: Junctionless multigate field-effect transistor. Appl Phys Lett 2009, 94: 053511. 10.1063/1.3079411View ArticleGoogle Scholar
- Wu YC, Chou CW, Tu CH, Lou JC, Chang CY: Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization. Appl Phys Lett 2005, 87: 143504. 10.1063/1.2076436View ArticleGoogle Scholar
- Hung MF, Wu YC, Tang ZY: High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory. Appl Phys Lett 2011, 98: 162108. 10.1063/1.3582925View ArticleGoogle Scholar
- Chen HB, Chang CY, Lu NH, Wu JJ: Characteristics of gate-all-around junctionless poly-Si TFTs with an ultrathin channel. IEEE Electron Device Lett 2013, 34: 7.View ArticleGoogle Scholar
- Kranti A, Yan R, Lee CW, Ferain I: Junctionless nanowire transistor (JNT): properties and design guidelines. 2010 Proceedings of the European Solid-State Device Research Conference: 14–16 Sept 2010; Sevilla 357.Google Scholar
- Linh Hong K: Comparison of embedded non-volatile memory technologies and their applications. 2009.http://www.kilopass.com/wp-content/uploads/2010/04/comparison_of_embedded_nvm.pdf Google Scholar
- Ito H, Namekawa T: Pure CMOS one-time programmable memory using gate-ox anti-fuse. Custom Integrated Circuits Conference 2004: 3–6 Oct 2004 469.Google Scholar
- Barsatan R, Man TY: A zero-mask one-time programmable memory array for RFID applications. Proceedings of the 2006 IEEE International Symposium on Circuits and Systems: 21–24 May 2006; Island of KosGoogle Scholar
- Houssa M, Tuominen M, Naili M, Afanasev V: Trap-assisted tunneling in high permittivity gate dielectric stacks. J Appl Phys 2000, 87: 12.View ArticleGoogle Scholar
- Chou AI, Lai KF, Kumar K, Chowdhury P: Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism. Appl Phys Lett 1997, 70: 25. 10.1063/1.119293View ArticleGoogle Scholar
- Register LF, Rosenbaum E, Yang K: Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices. Appl Phys Lett 1999, 74: 3.View ArticleGoogle Scholar
This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly credited.