Open Access

A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory

  • Mu-Shih Yeh1,
  • Yung-Chun Wu1Email author,
  • Kuan-Cheng Liu1,
  • Ming-Hsien Chung1,
  • Yi-Ruei Jhan1,
  • Min-Feng Hung1 and
  • Lun-Chun Chen1
Nanoscale Research Letters20149:603

https://doi.org/10.1186/1556-276X-9-603

Received: 27 June 2014

Accepted: 16 October 2014

Published: 6 November 2014

Abstract

This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. In the future, this device will be applied to multi-layer Si ICs in fully functional systems on panels, active-matrix liquid-crystal displays, and three-dimensional (3D) stacked flash memory.

Keywords

Single poly-Si Gate-all-around Junctionless Fin field-effect transistor One-time programming Nonvolatile memory Three-dimensional Flash memory

Background

Twin thin-film transistor (TFT) nonvolatile memory (NVM)[1, 2] tunnel oxide and blocking oxide were formed simultaneously as a ‘single poly-Si layer’. The simple process flow allows a logic circuit to be easily embedded in this device, reducing process costs. The coupling ratio of the memory can be easily controlled by setting the ratio T1/T2 according to the formula. Figure 1b shows the equivalent circuit of this single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) NVM:
Figure 1

Schematic and equivalent circuit of the single poly-Si JL-FinFET GAA NVM. (a) Schematic of the single poly-Si JL-FinFET GAA NVM with ten NWs and (b) its equivalent circuit. Two transistors, T1 (NW channel) and T2 (wide channel), are connected by a floating gate (FG), and the source and drain of T2 are connected as the controlling gate (CG). The simplified calculation of the voltage in floating gate is appended in (b).

V F G = C 2 / C 1 + C 2 × V G = W 2 / W eff + W 2 × V G = α G × V G
The single poly-Si GAA JL-FinFET NVM has a coupling ratio of 0.85, which is much larger than that of the conventional stacked memory. In programming, the electrons tunnel into T1 through the tunneling oxide. The tunneling oxide of nanowire (NW)-based NVM is surrounded by the gate electrode. To maximize the voltage drop in the tunnel oxide of T1, the gate capacitance of T2 (C2) must exceed the gate capacitance of T1 (C1). Hence, the NVM device with a high artificial gate coupling ratio (αG) exhibits a high program speed and can be operated at a low voltage. Noteworthily, the particular planar twin-TFT NVM structure enables the C1, C2, and αG to be easily designed. The device was designed to have a coupling ratio of 0.85 by setting T1/T2 = 1 μm/6 μm (Figure 2a). The single poly-Si GAA JL-FinFET NVM can be easily incorporated into SOI CMOS technology without additional processing[35].
Figure 2

SEM and TEM images of the single poly-Si JL-FinFET GAA NVM. (a) The top-view SEM image of the active region of single poly-Si JL-FinFET GAA NVM with gate length (Lg) = 0.1 μm. (b) The TEM image of cross-section of the single poly-Si JL-FinFET NVM with GAA-NWs. (c) The effective channel width (Weff) is 200 nm × 10 [(93 nm × 2 + 7 nm × 2) × 10)]. (d) The oxide/nitride layers are designed to be 4.5 nm thick/7.3 nm thick.

In this work, a JL channel[611] is introduced into the single poly-Si structure. The use of the JL channel enables the short channel effect (SCE) to be reduced and a simple implantation process to be used. The single poly-Si JL-FinFET NVM reduces the leakage current, according to Moore’s law, significantly reducing the development time and fabrication cost. JL NW devices with high doping concentrations in their channel and source/drain (S/D) regions have attracted much interest. The advantages of these devices over conventional inversion mode devices are (1) lack of need for an ultra-shallow S/D junction, which simplifies the fabrication process; (2) a low thermal budget, because of the elimination of the need for implant activation annealing after gate stack formation; and (3) concentration of the current of the JL device on the bulk of the semiconductor, which reduces the adverse effects of imperfect interfaces between the semiconductor and the insulator.

The channel is designed with a GAA structure to ensure that the gate can be effectively controlled[12, 13]. GAA devices have an on/off ratio of 107 and a subthreshold swing (SS) of 150 mV/decade, which can be easily obtained when the thickness of the JL channel is well controlled[14, 15].

The one-time programming (OTP) memory device can be programmed at high speed; it exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. Therefore, this work develops a high-performance single poly-Si GAA JL-FinFET NVM, which has high programming speed and excellent reliability.

Methods

In this work, a single poly-Si JL-FinFET NVM with an oxide/nitride layer is fabricated. Figure 1a schematically depicts the single poly-Si JL-FinFET NVM with ten NWs and the device has GAA-NWs. The gate electrodes of two TFTs are connected to form the floating gate (FG), while the source and drain of the larger TFT (T2) are connected to form the control gate.

The aforementioned devices were fabricated by initially growing a 400-nm-thick thermal oxide layer on 6-in. silicon wafers as substrates. A thin 50-nm-thick undoped amorphous-Si (a-Si) layer was then deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. The deposited a-Si layer was then solid-phase crystallized (SPC) at 600°C for 24 h in nitrogen ambient. A 2 × 1014 cm−2 dose of phosphorus was implanted and the device was then annealed to form the n-type active layer. The active device was patterned by electron beam (e-beam) direct writing and transferred by reactive ion etching (RIE). The device was dipped in hydrogen fluoride (HF) solution for 120 s to suspend the NWs in midair.

To enable the JL device to be controlled, the channel must be trimmed in the thickness direction. Therefore, the naked NWs can form by thermal oxidation which grew the 24-nm oxide layer and then dipped in HF for 100 s to remove the first sacrificial oxide layer. The dipped HF condition can keep the buried oxide sustain NWs (Figure 2c). Secondly, thermal oxidation is performed to produce a tunnel oxide layer with a thickness of 3 nm. Then, LPCVD is conducted to deposit a 7-nm-thick nitride layer as storage layer. The gate regions are formed by in situ doping with phosphorus ions to form the n-type poly gate. The channel of the device thus formed has a GAA structure.

On such devices, a 200-nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD. Next, the contact holes were defined and a 300-nm-thick Al-Si-Cu metallization was performed. Finally, the device was sintered at 400°C in nitrogen ambient for 30 min.

Results and discussion

Figure 2a shows the top-view scanning electron microscopic (SEM) image of the active region of a single poly-Si JL-FinFET GAA NVM with gate length (Lg) = 0.1 μm. Figure 2b presents a cross-sectional transmission electron microscopy (TEM) image of a single poly-Si JL-FinFET NVM with GAA-NWs. Figure 2c,d shows the effective channel width is 200 nm × 10 [(93 nm × 2 + 7 nm × 2) × 10)]. The oxide/nitride layers are designed to be 4.5 nm thick/7.3 nm thick as well as the entire device.To operate the memory, the device is programmed by Fowler-Nordheim (F-N) tunneling by applying 17 V, as presented in Figure 3. The memory window is opened to 5.2 V for 1 s. This device cannot be erased when a negative bias is applied, perhaps because of the high carrier density in the channel and the fact that the channel does not have sufficient holes to be able to erase. Figure 4a,b displays the programming speeds of the device GAA-NW and the planar device, respectively. The GAA-NW device has a higher programming speed than the planar device because of the field enhancement effect at corners of the oxide layer.
Figure 3

Program characteristics of the single poly-Si JL-FinFET GAA NVM. With F-N programming, the memory window opens to 5.2 V for 1 s. Erase is invalid.

Figure 4

Programming speed characteristics of the single poly-Si JL-FinFET NVM. Program speed characteristic of (a) JL-FinFET with GAA-NWs and (b) JL-FinFET with planar structures, respectively.

Recently, the embedded NVM has been extensively applied to different systems[16]. A device that can only be programmed once, which is called a ‘one-time programmable device’ , plays an important role in CMOS technology. OTP has always attracted much interest because of the ease of the process flow and its high performance, which reduce the cost of the process.

An OTP device[17, 18] cannot be repeatedly operated; it is used for its good retention. Figure 5 shows the retention testing of such a device with the GAA-NW structure programmed using the F-N operation. When a voltage of more than 23 V was applied for 1 s, independently of the temperature (from 85°C to 200°C), the device exhibited perfect retention. In a retention test, at least 95% of the original charge remained after 10 years. This excellent retention makes the device a good OTP device. The device exhibits perfect retention when large pulses are applied one at a time separately and consecutively, pushing electrons into the FG region or into deep traps in the silicon nitride.
Figure 5

Retention characteristics. Retention characteristics of the JL-FinFET GAA-NW device using different voltages and temperatures.

Figure 6 presents the energy band diagram in the retention state; Figure 6a shows the conventional FG memory devices. After a program cycle, some of the electrons will be stored in the interface trap between the channel and oxide, and these stored electrons induce the leakage current. Since the leaking possibility of the electrons is increasing, conventional FG memory devices are resulting in poor reliability and retention. Figure 6b shows the conditions for programming the device using voltages of less than 23 V. Some of the charges are stored in the shallow trapping layer of nitride or at the interface between the oxide and the nitride layer. Under high-temperature conditions, these charges may leak out by trap-assisted tunneling[19, 20] or direct tunneling[21] through the oxide, resulting in poor retention. In contrast, when the programming voltage is higher than 23 V for 1 s, charges that are trapped in the nitride may undergo trap-assisted tunneling, and all such charges are pushed into the FG region as shown in Figure 6c, because the nitride layer has many trap sites and the electron will encounter a high potential barrier when it is stored in the poly-Si region. Hence, the device in this work is favorable for OTP applications and exhibits excellent retention and reliability.
Figure 6

Energy band diagram in the retention state of the single poly-Si JL-FinFET GAA NVM. (a) The conventional FG memory devices. Band diagram of retention state for operation voltage (b) lower than 23 V for 1 s and (c) larger than 23 V for 1 s.

Conclusions

This work demonstrates the potential of the single poly-Si JL-FinFET GAA NVM for use in OTP operations and its easy embedding into logic circuits. The device can be programmed by FN tunneling but not easily erased, owing to the high dopant concentration. The GAA structure provides good control ability. The device exhibits excellent retention and the memory window can be maintained at 2 V after 108 s, with at least 95% of the original charge stored for more than 10 years. At 200°C, in a high-temperature retention test, the device exhibits better retention than at low temperature. Measurements demonstrate that the device has a lower fabrication cost and greater scalability than the conventional OTP memory. Therefore, the single poly-Si JL-FinFET GAA NVM is an effective embedded NVM for advanced logic technologies.

Declarations

Acknowledgements

The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under contract no. MOST 103-2221-E-007 -114 -MY3. The National Nano Device Laboratories is greatly appreciated for its technical support.

Authors’ Affiliations

(1)
Department of Engineering and System Science, National Tsing Hua University

References

  1. Yeh MS, Wu YC, Hung MF, Liu KC, Jhan YR, Chen LC, Chang CY: Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory. Nanoscale Res Lett 2013, 8: 331. 10.1186/1556-276X-8-331View ArticleGoogle Scholar
  2. Hung MF, Wu YC, Tsai TM, Chen JH, Jhan YR: Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory. Appl Phys Express 2012, 5: 121801. 10.1143/APEX.5.121801View ArticleGoogle Scholar
  3. Wu YC, Su PW, Chang CW, Hung MF: Novel twin poly-Si thin-film transistors EEPROM with trigate nanowire structure. IEEE Electron Device Lett 2008, 29: 1226.View ArticleGoogle Scholar
  4. Wu YC, Hung MF, Su PW: Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH3 plasma passivation. J Electrochem Soc 2011, 158: H578. 10.1149/1.3560576View ArticleGoogle Scholar
  5. Hung MF, Wu YC, Chang JJ, Chang-Liao KS: Twin thin-film transistor nonvolatile memory with an indium–gallium–zinc–oxide floating gate. Appl Phys Lett 2013, 34: 1.Google Scholar
  6. Li X, Han W, Wang H, Ma L, Zhang Y, Du Y, Yang F: Low-temperature electron mobility in heavily n-doped junctionless nanowire transistor. Appl Phys Lett 2013, 102: 223507. 10.1063/1.4809828View ArticleGoogle Scholar
  7. Rudenko T, Nazarov A, Ferain I, Das S, Yu R, Barraud S, Razavi P: Mobility enhancement effect in heavily doped junctionless nanowire silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 2012, 101: 213502. 10.1063/1.4767353View ArticleGoogle Scholar
  8. Sorée B, Magnus W, Vandenberghe W: Low-field mobility in ultrathin silicon nanowire junctionless transistors. Appl Phys Lett 2011, 99: 233509. 10.1063/1.3669509View ArticleGoogle Scholar
  9. Lee CW, Nazarov AN, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Doria RT, Colinge JP: Low subthreshold slope in junctionless multigate transistors. Appl Phys Lett 2010, 96: 102106. 10.1063/1.3358131View ArticleGoogle Scholar
  10. Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu RA, Nazarov AN, Doria RT: Reduced electric field in junctionless transistors. Appl Phys Lett 2010, 96: 073510. 10.1063/1.3299014View ArticleGoogle Scholar
  11. Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP: Junctionless multigate field-effect transistor. Appl Phys Lett 2009, 94: 053511. 10.1063/1.3079411View ArticleGoogle Scholar
  12. Wu YC, Chou CW, Tu CH, Lou JC, Chang CY: Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization. Appl Phys Lett 2005, 87: 143504. 10.1063/1.2076436View ArticleGoogle Scholar
  13. Hung MF, Wu YC, Tang ZY: High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory. Appl Phys Lett 2011, 98: 162108. 10.1063/1.3582925View ArticleGoogle Scholar
  14. Chen HB, Chang CY, Lu NH, Wu JJ: Characteristics of gate-all-around junctionless poly-Si TFTs with an ultrathin channel. IEEE Electron Device Lett 2013, 34: 7.View ArticleGoogle Scholar
  15. Kranti A, Yan R, Lee CW, Ferain I: Junctionless nanowire transistor (JNT): properties and design guidelines. 2010 Proceedings of the European Solid-State Device Research Conference: 14–16 Sept 2010; Sevilla 357.Google Scholar
  16. Linh Hong K: Comparison of embedded non-volatile memory technologies and their applications. 2009.http://www.kilopass.com/wp-content/uploads/2010/04/comparison_of_embedded_nvm.pdf []Google Scholar
  17. Ito H, Namekawa T: Pure CMOS one-time programmable memory using gate-ox anti-fuse. Custom Integrated Circuits Conference 2004: 3–6 Oct 2004 469.Google Scholar
  18. Barsatan R, Man TY: A zero-mask one-time programmable memory array for RFID applications. Proceedings of the 2006 IEEE International Symposium on Circuits and Systems: 21–24 May 2006; Island of KosGoogle Scholar
  19. Houssa M, Tuominen M, Naili M, Afanasev V: Trap-assisted tunneling in high permittivity gate dielectric stacks. J Appl Phys 2000, 87: 12.View ArticleGoogle Scholar
  20. Chou AI, Lai KF, Kumar K, Chowdhury P: Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism. Appl Phys Lett 1997, 70: 25. 10.1063/1.119293View ArticleGoogle Scholar
  21. Register LF, Rosenbaum E, Yang K: Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices. Appl Phys Lett 1999, 74: 3.View ArticleGoogle Scholar

Copyright

© Yeh et al.; licensee Springer. 2014

This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly credited.