TY - JOUR AU - Yeh, M. S. AU - Wu, Y. C. AU - Hung, M. F. AU - Liu, K. C. AU - Jhan, Y. R. AU - Chen, L. C. AU - Chang, C. Y. PY - 2013 DA - 2013// TI - Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory JO - Nanoscale Res Lett VL - 8 UR - https://doi.org/10.1186/1556-276X-8-331 DO - 10.1186/1556-276X-8-331 ID - Yeh2013 ER - TY - JOUR AU - Hung, M. F. AU - Wu, Y. C. AU - Tsai, T. M. AU - Chen, J. H. AU - Jhan, Y. R. PY - 2012 DA - 2012// TI - Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory JO - Appl Phys Express VL - 5 UR - https://doi.org/10.1143/APEX.5.121801 DO - 10.1143/APEX.5.121801 ID - Hung2012 ER - TY - JOUR AU - Wu, Y. C. AU - Su, P. W. AU - Chang, C. W. AU - Hung, M. F. PY - 2008 DA - 2008// TI - Novel twin poly-Si thin-film transistors EEPROM with trigate nanowire structure JO - IEEE Electron Device Lett VL - 29 UR - https://doi.org/10.1109/LED.2008.2005070 DO - 10.1109/LED.2008.2005070 ID - Wu2008 ER - TY - JOUR AU - Wu, Y. C. AU - Hung, M. F. AU - Su, P. W. PY - 2011 DA - 2011// TI - Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH3 plasma passivation JO - J Electrochem Soc VL - 158 UR - https://doi.org/10.1149/1.3560576 DO - 10.1149/1.3560576 ID - Wu2011 ER - TY - JOUR AU - Hung, M. F. AU - Wu, Y. C. AU - Chang, J. J. AU - Chang-Liao, K. S. PY - 2013 DA - 2013// TI - Twin thin-film transistor nonvolatile memory with an indium–gallium–zinc–oxide floating gate JO - Appl Phys Lett VL - 34 ID - Hung2013 ER - TY - JOUR AU - Li, X. AU - Han, W. AU - Wang, H. AU - Ma, L. AU - Zhang, Y. AU - Du, Y. AU - Yang, F. PY - 2013 DA - 2013// TI - Low-temperature electron mobility in heavily n-doped junctionless nanowire transistor JO - Appl Phys Lett VL - 102 UR - https://doi.org/10.1063/1.4809828 DO - 10.1063/1.4809828 ID - Li2013 ER - TY - JOUR AU - Rudenko, T. AU - Nazarov, A. AU - Ferain, I. AU - Das, S. AU - Yu, R. AU - Barraud, S. AU - Razavi, P. PY - 2012 DA - 2012// TI - Mobility enhancement effect in heavily doped junctionless nanowire silicon-on-insulator metal-oxide-semiconductor field-effect transistors JO - Appl Phys Lett VL - 101 UR - https://doi.org/10.1063/1.4767353 DO - 10.1063/1.4767353 ID - Rudenko2012 ER - TY - JOUR AU - Sorée, B. AU - Magnus, W. AU - Vandenberghe, W. PY - 2011 DA - 2011// TI - Low-field mobility in ultrathin silicon nanowire junctionless transistors JO - Appl Phys Lett VL - 99 UR - https://doi.org/10.1063/1.3669509 DO - 10.1063/1.3669509 ID - Sorée2011 ER - TY - JOUR AU - Lee, C. W. AU - Nazarov, A. N. AU - Ferain, I. AU - Akhavan, N. D. AU - Yan, R. AU - Razavi, P. AU - Yu, R. AU - Doria, R. T. AU - Colinge, J. P. PY - 2010 DA - 2010// TI - Low subthreshold slope in junctionless multigate transistors JO - Appl Phys Lett VL - 96 UR - https://doi.org/10.1063/1.3358131 DO - 10.1063/1.3358131 ID - Lee2010 ER - TY - JOUR AU - Colinge, J. P. AU - Lee, C. W. AU - Ferain, I. AU - Akhavan, N. D. AU - Yan, R. AU - Razavi, P. AU - Yu, R. A. AU - Nazarov, A. N. AU - Doria, R. T. PY - 2010 DA - 2010// TI - Reduced electric field in junctionless transistors JO - Appl Phys Lett VL - 96 UR - https://doi.org/10.1063/1.3299014 DO - 10.1063/1.3299014 ID - Colinge2010 ER - TY - JOUR AU - Lee, C. W. AU - Afzalian, A. AU - Akhavan, N. D. AU - Yan, R. AU - Ferain, I. AU - Colinge, J. P. PY - 2009 DA - 2009// TI - Junctionless multigate field-effect transistor JO - Appl Phys Lett VL - 94 UR - https://doi.org/10.1063/1.3079411 DO - 10.1063/1.3079411 ID - Lee2009 ER - TY - JOUR AU - Wu, Y. C. AU - Chou, C. W. AU - Tu, C. H. AU - Lou, J. C. AU - Chang, C. Y. PY - 2005 DA - 2005// TI - Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization JO - Appl Phys Lett VL - 87 UR - https://doi.org/10.1063/1.2076436 DO - 10.1063/1.2076436 ID - Wu2005 ER - TY - JOUR AU - Hung, M. F. AU - Wu, Y. C. AU - Tang, Z. Y. PY - 2011 DA - 2011// TI - High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory JO - Appl Phys Lett VL - 98 UR - https://doi.org/10.1063/1.3582925 DO - 10.1063/1.3582925 ID - Hung2011 ER - TY - JOUR AU - Chen, H. B. AU - Chang, C. Y. AU - Lu, N. H. AU - Wu, J. J. PY - 2013 DA - 2013// TI - Characteristics of gate-all-around junctionless poly-Si TFTs with an ultrathin channel JO - IEEE Electron Device Lett VL - 34 UR - https://doi.org/10.1049/el.2012.3812 DO - 10.1049/el.2012.3812 ID - Chen2013 ER - TY - STD TI - Kranti A, Yan R, Lee CW, Ferain I: Junctionless nanowire transistor (JNT): properties and design guidelines. 2010 Proceedings of the European Solid-State Device Research Conference: 14–16 Sept 2010; Sevilla 357. ID - ref15 ER - TY - CHAP AU - Linh Hong, K. PY - 2009 DA - 2009// BT - Comparison of embedded non-volatile memory technologies and their applications ID - Linh Hong2009 ER - TY - STD TI - Ito H, Namekawa T: Pure CMOS one-time programmable memory using gate-ox anti-fuse. Custom Integrated Circuits Conference 2004: 3–6 Oct 2004 469. ID - ref17 ER - TY - STD TI - Barsatan R, Man TY: A zero-mask one-time programmable memory array for RFID applications. Proceedings of the 2006 IEEE International Symposium on Circuits and Systems: 21–24 May 2006; Island of Kos ID - ref18 ER - TY - JOUR AU - Houssa, M. AU - Tuominen, M. AU - Naili, M. AU - Afanasev, V. PY - 2000 DA - 2000// TI - Trap-assisted tunneling in high permittivity gate dielectric stacks JO - J Appl Phys VL - 87 UR - https://doi.org/10.1063/1.373587 DO - 10.1063/1.373587 ID - Houssa2000 ER - TY - JOUR AU - Chou, A. I. AU - Lai, K. F. AU - Kumar, K. AU - Chowdhury, P. PY - 1997 DA - 1997// TI - Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism JO - Appl Phys Lett VL - 70 UR - https://doi.org/10.1063/1.119186 DO - 10.1063/1.119186 ID - Chou1997 ER - TY - JOUR AU - Register, L. F. AU - Rosenbaum, E. AU - Yang, K. PY - 1999 DA - 1999// TI - Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices JO - Appl Phys Lett VL - 74 UR - https://doi.org/10.1063/1.123060 DO - 10.1063/1.123060 ID - Register1999 ER -