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# Graphene nanoribbon field-effect transistor at high bias

*Nanoscale Research Letters*
**volume 9**, Article number: 604 (2014)

## Abstract

Combination of high-mean free path and scaling ability makes graphene nanoribbon (GNR) attractive for application of field-effect transistors and subject of intense research. Here, we study its behaviour at high bias near and after electrical breakdown. Theoretical modelling, Monte Carlo simulation, and experimental approaches are used to calculate net generation rate, ionization coefficient, current, and finally breakdown voltage (BV). It is seen that a typical GNR field-effect transistor's (GNRFET) breakdown voltage is in the range of 0.5 to 3 V for different channel lengths, and compared with silicon similar counterparts, it is less. Furthermore, the likely mechanism of breakdown is studied.

## Background

Scaling in CMOS technology has been the key action to improve the power and performance of field-effect transistors [1]. As a result, there is a continuous need for thinner and shorter channels to resolve problems such as short channel effects in modern transistors. However, this scaling trend could not continue for long with silicon as the channel material. Recently, graphene has been introduced as an alternative for silicon hoping that this trend could go on further. But the short channel and high-mean free path of graphene up to 400 nm [2] result in high ionization rate and breakdown at high biases. Therefore, it is important to study the breakdown in graphene-based transistors.

Breakdown current density in graphene has been reported number of times mostly to study their application in on-chip electrical interconnects using several experimental approaches. In [3], mechanically exfoliated graphene nanoribbons (GNRs) were found to display an impressive current-carrying capacity of more than 10^{8} A/cm^{2} for the widths down to 16 nm. In addition, breakdown voltage (BV) is estimated to be around 2.5 V for GNRs with widths of 22 nm. Chemical vapour deposition (CVD) was used by Lee et al. [4] to fabricate multilayer graphene sheets having an average thickness of 10 to 20 nm. They reported the breakdown current densities of up to 4 × 10^{7} A/cm^{2}. In addition, graphene wires with widths of 1 and 10 μm and lengths from 2 to 1,000 μm have been fabricated, and the breakdown voltage is reported to be around 8 V. Epitaxial graphene developed on silicon carbide is studied in terms of breakdown current in [5]. They prepared Hall bar structures of different sizes (*W* =0.5 to 5 μm, *L* =8 to 25 μm) by e-beam lithography, and maximum current density, mobility, and charge carrier density are measured. It is reported that the graphene film breaks down at a critical current density of 4 to 6 mA/μm. In another work, the BV of GNR field-effect transistor (GNRFET) is reported to be in the range from 0.25 to 0.65 V for 50-nm GNR with widths from 3 to 6 nm [6]. They used analytical approach to calculate the breakdown voltage and ionization coefficient in double-gate GNRFET. In modelling, Gauss's law and Poisson's equation [6–8] were applied to derive surface potential equation and the lucky drift theory to calculate the ionization coefficient [6]. However, they did not take the effect of ionization coefficient into account for surface potential modelling, which makes their model inaccurate for GNR. In addition, they used Monte Carlo approach to simulate ionization coefficient, while we extend the approach to calculate net generation rate. The effect of carrier generation once used in graphene field-effect transistor in [9] is different with our work in two ways: first, we study the GNRFET, and second, in this paper, we measure and model the breakdown voltage and current at high bias near breakdown, while that paper only derives the current.

## Methods

### Breakdown of GNRFET

Figure 1 shows the device used for modelling and fabrication in this project. The silicon substrate serves as the back gate. Identification of graphene flakes is done using optical approach and Raman spectroscopy. Drain, source, and gate contacts are patterned by several steps of electron beam lithography followed by metal deposition, and a HfO_{2} layer is formed by low-temperature atomic layer deposition (ALD), which is used to form SiO_{2}, too.

We start the modelling by electron and hole current density 1D continuity in graphene sheet channel yielding

where *α*_{i} is the electron generation rate due to ionization, *J*_{p} and *J*_{n} are current densities of holes and electrons, respectively, and *q* is the electron charge. The generation rate is normally ignored in silicon devices; however, according to [10], in graphene, this parameter is not ignorable. Integrating over Equation 1 results in

where *I* is the total channel current and *I*_{n} and *I*_{p} are electron and hole currents, respectively. Using charge equation, *Q*_{+} − *Q*_{−} = ± *C*_{
top
}(*V*_{
gt
} − *V*_{
bg
} − *φ*(*y*)), one can write

where ${v}_{\mathrm{d}}=\frac{\mu E\left(y\right)}{1+E\left(y\right)/{E}_{\mathrm{c}}}$ is the drift velocity, *μ* is mobility, *E*(*y*) is the electric filed, *E*_{c} is the critical electric field, *φ*(*y*) is surface potential, *V*_{bg} and *V*_{gt} are back- and top-gates, respectively, and *C*_{top} *= C*_{q}*C*_{ox} / *C*_{q} + *C*_{ox}, where *C*_{ox} and *C*_{q} are classic and quantum capacitances, respectively, of the gate given by *C*_{ox} *= ϵ*_{ox} / *t*_{ox} and *C*_{q} =2 *μF*/cm^{2}, respectively, with *ϵ*_{ox} being oxide dielectric constant.

Therefore, drain current equation could be written by integrating from source (*y* =0) to position *y* along the channel over Equation 3. As a result, we have

from which the surface potential is written as

where total current *I* according to [11] could be replaced by ${I}_{\mathrm{d}}=Wq{V}_{\mathrm{d}\mathrm{s}}{\left({\displaystyle {\int}_{0}^{L}\frac{E\left(y\right)}{n\left(y\right){\upsilon}_{d}}}\right)}^{-1}$, where *n*(*y*) is the carrier concentration of GNR and *V*_{ds} is the drain-source voltage.

Therefore, by using *φ*(*L*_{d}) = *V*_{sat}, where *V*_{sat} is the drain saturation voltage, one can write the equation of the saturation region length (*L*_{d}) as

Finally, applying avalanche breakdown condition [12], the breakdown voltage can be numerically calculated from $\int}_{0}^{{L}_{\mathrm{d}}}\alpha dx=1\text{,$ where *α* is the ionization coefficient calculated by Monte Carlo simulation.

### Monte Carlo simulation

Two scattering mechanisms of (i) elastic scattering by acoustic phonons, which is the dominant scattering mechanism at low carrier energies in GNR [13], and (ii) inelastic scattering via emitting an optical phonon of energy *ℏω*_{op}, which is the dominant scattering mechanism at high energies [13], are considered to be influential on the carrier trajectory. They are characterized by the associated individual mean free paths *λ*_{e} and *λ*_{ie} , respectively. The impact ionization takes place immediately after the carrier builds the kinetic energy equal to the ionization threshold *E*_{t}. The impact ionization coefficient is defined as *α* =1 / *Z*[14], where *Z* is the average distance travelled by the carrier in the field direction prior to the ionization. We use a self-scattering approach, which introduces a fictitious forward scattering in order to eliminate solving integral equations in every Monte Carlo step. The self-scattering rate *R*_{ss} is calculated from *R*_{ss} = *υ*_{
g
} / *λ*, where *λ* =1 / *λ*_{
m
} +1 / *λ*_{
ie
}, where *λ*_{m} and *λ*_{ie} are the momentum and energy mean free path. Free flight time (*dt*) is calculated from *dt* = −1 / *R*_{ss} ln(*r*), where *r* is a random number between 0 and 1. The wavevector and position vector ** X** are given by

*d*

**=**

*k**q*

*F**dt*/

*ℏ*and $d\mathit{k}=q\mathit{F}dt\phantom{\rule{0.12em}{0ex}}/\phantom{\rule{0.12em}{0ex}}\hslash \phantom{\rule{0.12em}{0ex}}\mathrm{and}\phantom{\rule{0.15em}{0ex}}\mathit{X}=\mathit{k}\frac{\hslash dt}{m}+q\mathit{F}d{t}^{2}/2m$, respectively. The kinetic energy of GNR is calculated from

*E*

_{k}=

*ℏ*

^{2}

*k*^{2}/

*m*∗, where

*m** is the effective mass of GNR. If

*E*

_{k}=

*ℏω*

_{op}, then

*R*

_{ie}is assigned a non-zero value. For elastic or inelastic scatterings, the orientation of

**is changed, while for self-scatterings, the**

*k***vector remains unchanged. Finally, the net generation rate due to impact ionization could be calculated from**

*k**α*=

*n*

_{2 D}(

*L*−

*x*) /

*t*, where

*n*

_{2D}is the two-dimensional carrier concentration.

## Results and discussion

In order to calculate BV, firstly, we need to know the values of net generation rate *α*_{i} and ionization coefficient *α*, which are simulated using the Monte Carlo approach presented. The values of *α*_{i} versus lateral electric field at different gate voltages are shown in Figure 2. In addition, in Figure 3, the ionization coefficient of GNR at different ionization threshold energies is depicted. Comparing silicon (extracted from [12, 15, 16]) with GNR shows that the ionization event in GNR is much more than that of silicon, which is attributed to its high-mean free path resulting in early velocity saturation of carriers. The solid lines in these two figures show the simulated data using Monte Carlo, and the red dots are the modelling data from [6]. There is discrepancy between the two approaches. In the modelling, the energy and momentum mean free time (*τ*_{E} and *τ*_{m}) are used to calculate the probability of energy and momentum relaxing collisions. For simplicity, it has been assumed that drift velocity is not a function of energy. In addition, the energy mean free time is calculated from ${\tau}_{\mathrm{E}}\phantom{\rule{0.5em}{0ex}}=\frac{E{\tau}_{\mathrm{m}}}{\hslash {w}_{\mathrm{op}}}$ since it has been assumed that the dominant scattering mechanism in graphene is phonon scattering ignoring acoustic phonon scattering mechanism, while in the Monte Carlo approach, it has been taken into account and drift velocity is a function of energy.

Next, we measure the drain current and compare with the modelling data in Figure 4. The markers show the experimental data, and the solid lines show the modelling data at different drain and gate voltages. There is a sudden current stop showing breakdown, which points to Joule heating as the likely mechanism of breakdown and a rise in current before current stop, which we associated to three phenomena of self-amplifying excess carrier generation caused by ionization, substrate contribution in current at high temperature, and generation of more conducting channels. Using current data at different conditions, the BV for different devices is obtained and shown in Figures 5 and 6. In Figure 5, four devices are fabricated and used with 50-, 100-, 150-, and 200-nm channel lengths at 0.4-V gate voltage. It is found that longer channel results in higher breakdown voltage ranging from almost 0.45 V for 50-nm to 1.65 V for 200-nm devices. The experimental data shown by red dots agree with the modelling data shown by solid lines. The experimental data from similar silicon-based devices are also shown in this figure. It is seen that GNR breaks down at lower voltages, which is the sign of ballistic carrier transport in graphene, resulting in hot carriers. In addition, in Figure 6, the gate voltage is changed from 0.2 to 1.4 V to examine its effect on the breakdown voltage. It is seen that the breakdown voltage could be 1.4 V for a 100-nm device at 0.2-V gate voltage. In addition, the theoretical data from [5] for breakdown of a typical single-gate device is shown by blue triangles. In theory, the effect of substrate and heating process has not been considered which we think is the reason for the small discrepancy between the theoretical and experimental data.

## Conclusions

The breakdown of graphene nanoribbon transistors was studied experimentally and theoretically in this report. Monte Carlo simulation was employed to simulate ionization rate and net generation rate. Then, the current is modelled and finally the breakdown voltage. In addition, we fabricated four devices, measured the breakdown voltage and current, and compared the voltage and current with those of the modelling data. A sudden rise and then a sudden stop were seen in the current profile which we associated with excess carrier generation and Joule heating, respectively. The breakdown of 50- to 200-nm devices was reported to be in the range of 0.5 to 3 V, which is less than that of counterpart silicon devices.

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## Acknowledgements

The authors would like to acknowledge the financial support from the Research University grant of the Ministry of Higher Education (MOHE), Malaysia, under Project Q.J130000.21A2.01E61 and Q.J130000.2523.05H23. Also, we would like to thank the Research Management Center (RMC) of Universiti Teknologi Malaysia (UTM) for providing an excellent research environment in which to complete this work. In addition, we would like to thank Sharif University of Technology for helping us fabricate the devices.

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### Competing interests

The authors declare that they have no competing interests.

### Authors’ contributions

MG carried out the modelling part. RI made a major revision of the paper and led the team. MS, MK, and MG contributed in the fabrication and measurement, and AAM did the Monte Carlo simulations. All authors read and approved the final manuscript.

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### Cite this article

Ghadiry, M., Ismail, R., Saeidmanesh, M. *et al.* Graphene nanoribbon field-effect transistor at high bias.
*Nanoscale Res Lett* **9, **604 (2014) doi:10.1186/1556-276X-9-604

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### Keywords

- Graphene
- High bias
- Current
- Breakdown
- Model
- Fabrication