Figure 1From: Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface trapsThe RIT simulation technique for the bulk FinFET devices. (a) and (a’) are the device structures. (b)-(b”’) are the distribution of ITs. (c) and (c’) illustrate the IT planes. (d) shows the individual trap’s density versus the trap’s energy.Back to article page