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Figure 7 | Nanoscale Research Letters

Figure 7

From: Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

Figure 7

Barrier height fluctuation induced by RITs for the studied devices with high D it. n-type HKMG (a) bulk FinFET and (b) planar MOSFET devices. The devices are under off-state condition, where VG = Vs = VB = 0 V and VD = 0.6 V for the FinFET and VG = Vs = VB = 0 V and VD = 0.8 V for the planar MOSFET. (c) The Ioff-Ion plot used to explain the position and number effects of RITs.

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