Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
© Cheng et al.; licensee Springer. 2014
Received: 30 June 2014
Accepted: 26 November 2014
Published: 11 December 2014
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the Ion/Ioff current ratio is over 108 A/A for Lg = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust Vth in multi-Vth circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
Recently, the concept of the junctionless (JL) field-effect transistor (FET), which contains a heavily, uniformly, and homogeneously doping species in the channel and source/drain (S/D), has been intensively studied [1–4]. The JL device is intrinsically a gated resistor, i.e., a resistor with a gate for controlling the carrier density and the current flow. The advantages of JL devices include (1) avoidance of the use of an ultra-shallow source/drain junction, which greatly simplifies the process flow, (2) low thermal budgets owing to implant activation annealing after the gate stack formation is eliminated, and (3) the current transport is in the bulk of the semiconductor, which reduces the impact of imperfect semiconductor/insulator interfaces. These features have also been demonstrated with poly-Si thin-film transistor (TFT) [5–7], which are suitable for monolithic three-dimensional (3D) vertically stacked integrated circuits (ICs), which continue the applicability of Moore’s law . However, the JL channel thickness should be thin enough to turn off the JL devices. This limits the saturation current of the junctionless thin-film transistor (JL-TFT) [7, 9]. Meanwhile, it adversely increases series resistance in the S/D and decreases drain current. In order to conquer this issue, the raised source-and-drain (raised S/D) structure is used for this works.
In this work, the thin-channel structure trimmed by oxidation and HF is used for turning off the devices, and the raised S/D structure is built for high saturation current. A dual-gate structure can be applied in multi-threshold voltage (multi-Vth) applications , and its temperature is discussed for the p-type raised S/D JL-TFTs.
Device fabrication and experiment
Results and discussion
This work realizes the p-type raised S/D JL-TFTs and dual-gate structure. In our devices, the thin channel formed by the oxidation trimming process and raise S/D structure are used. Due to these two ideas, the high on current (>1 μA/μm), low off current (10−14 A), and small SS (100 mV/decade) could be achieved. It is a promising structure to get a good-performance JL device and conquer the low-Ion issue of JL devices. The temperature of the raised S/D devices is discussed for the electrical parameters (SS, Vth). It is worthy to notice that the dual-gate structure can be used to adjust Vth to fulfill the multi-Vth circuit designs. The devices are highly promising for future further scaling and 3D stacked IC applications.
The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under Contract No. MOST 103-2221-E-007 -114 -MY3. The National Nano Device Laboratories is greatly appreciated for its technical support.
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