Impact of program/erase operation on the performances of oxide-based resistive switching memory
© Wang et al.; licensee Springer. 2015
Received: 14 November 2014
Accepted: 29 December 2014
Published: 5 February 2015
Further performance improvement is necessary for resistive random access memory (RRAM) to realize its commercialization. In this work, a novel pulse operation method is proposed to improve the performance of RRAM based on Ti/HfO2/Pt structure. In the DC voltage sweep of the RRAM device, the SET transition is abrupt under positive bias. If current sweep with positive bias is utilized in SET process, the SET switching will become gradual, so SET is current controlled. In the negative voltage sweep for RESET process, the change of current with applied voltage is gradual, so RESET is voltage controlled. Current sweep SET and voltage sweep RESET shows better controllability on the parameter variation. Considering the SET/RESET characteristics in DC sweep, in the corresponding pulse operation, the width and height of the pulse series can be adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation in which both the width and height of program/erase pulse are simply kept constant which would lead to unnecessary damage to the device. In our new method, in each program or erase operation, a series of pulses with the width/height gradually increased are made use of to fully finish the SET/RESET switching but no excessive stress is generated at the same time, so width/height-controlled accurate SET/RESET can be achieved. Through the operation, the uniformity and endurance of the RRAM device has been significantly improved.
Thanks to the increasing demand from portable electronic products like smartphones, cameras, and laptops, the demand for solid-state memories has been increasing rapidly in recent years. However, in the further scaling down, the traditional flash memory is facing more and more problems due to its physical limitations. Although innovations in cell structure and device materials may help extend flash memory for another couple of technology nodes, alternative candidates must be explored for future non-volatile memory (NVM) applications. Among various candidates, resistive random access memory (RRAM) is the most promising one for future high-density NVM application, owning to its characteristics of simple cell structure, fast program/erase (P/E) speed, excellent scalability, low operation power consumption, and good compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process [1-5]. However, in order to meet the practical application requirements, the performances of RRAM demonstrated to date still need improvements in the following areas: (1) effective control of high and low resistance state; (2) minimization of the variations of resistive switching parameters. Some approaches have been proposed to improve the operation test method of RRAM. Nevertheless, few works systematically studied the detailed influence of DC and pulse program/erase operations on the performances of oxide-based RRAM. In this work, aiming at addressing the above challenges, we try to elucidate the impact of P/E operation on the performances through comprehensive device characterizations and to explore possible solutions through innovations in test and operation methods.
For the necessity of plenty of DC and pulse measurement, stable valence change mechanism (VCM) devices with Ti/HfO2/Pt structure [5-12] is made use of in this work. In the DC positive voltage sweep the SET transition is abrupt, but it becomes gradual under current sweep. The RESET process is gradual in negative voltage sweep. So SET and RESET are current and voltage controlled, respectively. Combining positive current sweep SET and corresponding negative voltage sweep RESET operation, stable and uniform distributions of on-state and off-state resistance can be obtained. Gaining inspiration from the DC SET/RESET characteristics, we proposed a novel pulse operation scheme, i.e. the width and height of the pulse series are adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation with single constant program/erase pulse. Thus, accurate SET/RESET controlled by pulse width/height can be achieved through our new method. As a result of the new method, the uniformity and endurance of the RRAM device has been significantly improved.
Resistive switching memory devices with Ti/HfO2/Pt structure were fabricated as follows. First, after the standard chemical cleaning of the silicon substrate, a SiO2 film with a thickness of 100 nm was thermally grown through dry oxidation method. Then, Ti/Pt bilayer with thickness of 30/70 nm was sequentially deposited by e-beam evaporation to act as the bottom electrode (BE). Next, a high-quality 8-nm-thickness HfO2 resistive switching layer was grown by atom layer deposition (ALD) technology, which has the advantage of well controlling on the deposition parameters and excellent deposition uniformity. Finally, the 10/70-nm-thickness Ti/Pt bilayer or 70-nm-thickness Cu film was prepared by e-beam evaporation and then patterned by lift-off process to form the top electrode (TE). The area of TE is defined as 100 × 100 μm2. The DC electrical characteristics of the devices were measured by Keithley 4200-SCS semiconductor characterization system, where the Pt BE was grounded while the bias voltage was applied on the Ti/Pt or Cu TE. In the traditional pulse measurement, a single pulse was usually employed to fulfill the SET/RESET operation, and a small read pulse or a visual tool was used to verify if the SET/RESET is completed and to measure the switching time. In the height/width-adjusting pulse operation measurement, Keithley 4205-PG2 pulse generator was used to generate program/erase pulse series by an automatic procedure, and the device states were read by Keithley 4200-SCS. A matrix Keithley 707A is used to carry out the switching between the pulse program/erase operation and DC read operation.
Results and discussion
The distributions of R on and R off under different operation modes
VS_SET and VS_RESET
CS_SET and CS_RESET
VS_SET and CS_RESET
CS_SET and VS_RESET
SP_P and SP_E
AP_P and AP_E
We have investigated the impact of DC and pulse program/erase operation on the uniformity and endurance performances of Ti/HfO2/Pt-based RRAM device. Appropriate program/erase conditions are necessary to acquire the uniform resistive switching. A width-adjusting program and the height-adjusting erase pulse operation method are proposed. Our new method is advantageous to obtain the moderate program/erase operation in each cycle, without any inadequate operation and over operation. Thus, the endurance performance of the device is greatly improved. Based on our method, some technical solutions to improve the endurance of the RRAM can be developed.
This work was supported by the National Natural Science Foundation of China under Grant Nos. 61322408, 61221004, 61422407, 61334007, and 61274091, the National Basic Research Program of China under Grant No. 2011CBA00602, and the National High Technology Research Development Program under Grant No. 2014AA032900.
- Waser R, Aono M. Nanoionics-based resistive switching memories. Nat Mater. 2007;6:833–40.View ArticleGoogle Scholar
- Yang JJ, Strukov DB, Stewart DR. Memristive devices for computing. Nat Nanotechnol. 2013;8:13–24.View ArticleGoogle Scholar
- Pan F, Gao S, Chen C, Song C, Zeng F. Recent progress in resistive random access memories: materials, switching mechanisms, and performance. Mater Sci Eng R. 2014;83:1–59.View ArticleGoogle Scholar
- Wong H-SP, Lee H-Y, Yu S, Chen Y-S, Wu Y, Chen P-S, et al. Metal-oxide RRAM. Proc IEEE. 2012;100:1951–70.View ArticleGoogle Scholar
- Waser R, Dittmann R, Staikov G, Szot K. Redox-based resistive switching memories-nanoionic mechanisms, prospects, and challenges. Adv Mater. 2009;21:2632–63.View ArticleGoogle Scholar
- Lee H-Y, Chen P-S, Wu T-Y, Wang C-C, Tzeng P-J, Chen F, et al. An ultrathin forming-free HfO x resistance memory with excellent electrical performance. IEEE Electron Device Lett. 2010;31:1473–5.View ArticleGoogle Scholar
- Chen H-Y, Wu S-C, Jiang Z, Yu S, Hou T-H, Wong H-SP, et al. Improved multi-level control of RRAM using pulse-train programming. Symp VLSI Technol. 2014;1:2.Google Scholar
- Chen PS, Wu TY, Chen YS, Wang CC, Tzeng PJ, Lin CH, et al. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM. IEEE Int Electron Devices Meet Tech Dig. 2008;1:4.Google Scholar
- Chen B, Gao B, Fang Z, Fu YH, Yang JQ, Liu LF, et al. Improvement of endurance degradation for oxide based resistive switching memory devices correlated with oxygen vacancy accumulation effect. Proc Int Reliab Phys Symp. 2012;4:1–4.Google Scholar
- Lanza M. A review on resistive switching in high-k dielectrics: a nanoscale point of view using conductive atomic force microscope. Materials. 2014;7:2155–82.View ArticleGoogle Scholar
- Chu T-J, Chang T-C, Tsai T-M, Wu H-H, Chen J-H, Chang K-C, et al. Charge quantity influence on resistance switching characteristic during forming process. IEEE Electron Device Lett. 2013;34:502–4.View ArticleGoogle Scholar
- Chang K-C, Tsai T-M, Chang T-C, Wu H-H, Chen J-H, Syu Y-E, et al. Characteristics and mechanisms of silicon-oxide-based resistance random access memory. IEEE Electron Device Lett. 2013;34:399–401.View ArticleGoogle Scholar
- Luo W-C, Liu J-C, Feng H-T, Lin Y-C, Huang J-J, Lin K-L, et al. RRAM set speed-disturb dilemma and rapid statistical prediction methodology. IEEE Int Electron Devices Meet Tech Dig. 2012;9:5.1–4.Google Scholar
- Luo W-C, Liu J-C, Lin Y-C, Lo C-L, Huang J-J, Lin K-L, et al. Statistical model and rapid prediction of RRAM SET speed-disturb dilemma. IEEE Trans Electron Devices. 2013;60:3760–6.View ArticleGoogle Scholar
- Suñé J, Tous S, Wu EY. Analytical cell-based model for the breakdown statistics of multilayer insulator stacks. IEEE Electron Device Lett. 2009;30:1359–61.View ArticleGoogle Scholar
- Kim SY, Roy K. Physics-based compact modeling for statistics of successive breakdown in ultra-thin oxides. IEEE T Nanotechnol. 2014;2366379Google Scholar
- Raghavan N, Pey KL, Wu X, Liu W, Bosman M. Percolative model and thermodynamic: analysis of oxygen-ion-mediated resistive switching. IEEE Electron Device Lett. 2012;33:712–4.View ArticleGoogle Scholar
- Degraeve R, Roussel P, Goux L, Wouters D, Kittl J, Altimime L, et al. Generic learning of TDDB applied to RRAM for understanding of conduction and switching mechanism through multiple filaments. IEDM Tech Dig. 2010; 28.4.1–4. doi:10.1109/IEDM.2010.5703438.Google Scholar
- Long S, Cagli C, Ielmini D, Liu M, Suñé J. Analysis and modeling of resistive switching statistics. J Appl Phys. 2012;111:074508.View ArticleGoogle Scholar
- Long S, Lian X, Ye T, Cagli C, Perniola L, Miranda E, et al. Cycle-to-cycle intrinsic RESET statistics in HfO2-based unipolar RRAM devices. IEEE Electron Device Lett. 2013;34:623–5.View ArticleGoogle Scholar
- Zhang W, Wang C, Liu G, Wang J, Yu C, Li R-W. Structural effect on the resistive switching behavior of triphenylamine-based poly(azomethine)s. Chem Commun. 2014;50:11496–9.View ArticleGoogle Scholar
- Long S, Lian X, Cagli C, Cartoixà X, Rurali R, Miranda E, et al. Quantum-size effects in hafnium-oxide resistive switching. Appl Phys Lett. 2013;102:183505.View ArticleGoogle Scholar
- Ielmini D, Cagli C, Nardi F. Physical models of size-dependent nanofilament formation and rupture in NiO resistive switching memories. Nanotechnology. 2011;22:254022.View ArticleGoogle Scholar
- Ielmini D, Nardi F, Balatti S. Evidence for voltage-driven set/reset processes in bipolar switching RRAM. IEEE Trans Electron Devices. 2012;59:2049–56.View ArticleGoogle Scholar
- Larentis S, Nardi F, Balatti S, Gilmer DC, Ielmini D. Resistive switching by voltage-driven ion migration in bipolar RRAM - part II: modeling. IEEE Trans Electron Devices. 2012;59:2468–75.View ArticleGoogle Scholar
- Xu DL, Xiong Y, Tang MH, Zeng BW, Xiao YG. Bipolar and unipolar resistive switching modes in Pt/Zn0.99Zr0.01O/Pt structure for multi-bit resistance random access memory. Appl Phys Lett. 2014;104:183501.View ArticleGoogle Scholar
- Liu J-C, Wang I-T, Hsu C-W, Luo W-C, Hou T-H. Investigating MLC variation of filamentary and non-filamentary RRAM. Symp VLSI Technol. 2014;1:2.Google Scholar
- Zangeneh M, Joshi A. Design and optimization of nonvolatile multibit 1T1R resistive RAM. Symp VLSI Technol. 2013;22:1815–28.Google Scholar
- Yu S, Wu Y, Wong H-SP. Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory. Appl Phys Lett. 2011;98:103514.View ArticleGoogle Scholar
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly credited.