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Figure 3 | Nanoscale Research Letters

Figure 3

From: Impact of program/erase operation on the performances of oxide-based resistive switching memory

Figure 3

The testing schematic of pulse operation method. (a) The test circuit of our new pulse operation method. Pulses with width or height increased by the automatic procedure are applied to finish the program or erase operation, respectively. (b) Schematic diagram of one complete erase process with height-adjusting pulse operation. (c) Schematic diagram of one complete program cycle of width-adjusting pulse operation. (d) A detailed flow chart of the program method.

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