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Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants


In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16-nm-gate trapezoidal bulk fin-type field effect transistor (FinFET) devices. The fixed top-fin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed top-fin width, we explore the impact of geometry and RDF on the on-/off-state current and the threshold voltage (V th) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the off-state current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the short-channel effect and V th variation degrade as the fin angle is getting smaller. The magnitude of the normalized σV th increases 7% when the fin angle decreases from 90° to 70°.


Scaling down the CMOS technology node beyond the sub-20 nm causes the transistor to go through a transition from planar to multi-gate FETs such as bulk fin-type field effect transistors (FinFETs) because of the requirement of better gate control and suppression on short-channel effects (SCEs) [1-3]. In addition to the improvement on DC characteristics of individual device, however, continuously scaling not only overcomes challenges on fabrication but also suppresses systematic variation and random effects [4,5]. In practical fabrication, it is difficult to obtain uniform thickness along the height of the fin channel due to limitations in process technology [6]. The actual fins channel may be fabricated as trapezoidal shape and degrade the device performance by significant SCEs. For variability issues, there are many serious fluctuation sources such as random dopant fluctuation (RDF) [7], work-function fluctuation [8], interface trap fluctuation [9], and the line edge roughness [10]. For low-standby-power device technologies and applications, channel doping is still needed to adjust the threshold voltage (V th) and RDF has been shown as the major source of variations for high-Κ metal gate (HKMG) bulk FinFET devices [11] among various fluctuation factors. Recent researches on RDF and fin-shape effects were reported for FinFET devices; however, the studies on FinFET’s RDF were only considered for devices with a rectangular-shape fin channel [12]. However, the channel fin is not always with an ideal shape owing to process challenges. To the best of our knowledge, a research which simultaneously considers the aforementioned issues has not been well investigated yet.

In this study, we explore the RDF on DC characteristics of 16-nm-gate trapezoidal bulk FinFETs with the fixed top-fin width (W top) condition. We further intensively analyze the on-/off-state current characteristic and V th’s fluctuation of the 16-nm-gate trapezoidal HKMG bulk FinFET. The article is organized as follows. The ‘Methods’ section introduces the simulation technique for studying the RDF on trapezoidal bulk FinFET devices with different fin angles and the same W top. The ‘Results and discussion’ section focuses mainly on the analysis and discussion of characteristic fluctuation from RDF of 16-nm-gate trapezoidal HKMG bulk FinFET devices. Finally, we draw conclusions and suggest future work.


The device configuration and simulation technique

Figure 1a shows various TEM views of realistic shape of fabricated two-channel fin in 16-nm technological node. Due to the process capabilities, the fin angles θ 1 and θ 2, as shown in these two images, may vary with the lithography and etching, etc. Therefore, devices with different trapezoidal shapes are fabricated. In this study, we assume the top-fin width is fixed at 8 nm for the 16-nm-gate HKMG bulk FinFET devices. Figure 1b shows the schematic cross-section view of channel fin for the identical-W top setting. The fin angle (θ) is thus defined as the angle between the bottom line and sidewall and ranges from 70° to 90°. Besides the fixed W top, the channel doping concentration, which means the needed number of impurity in the channel region increases when the fin angle is getting smaller, is set the same for all simulation cases.

Figure 1
figure 1

TEM and schematic cross-section views of channel fin. (a) A TEM view of realistic shape of fabricated channel fin to show the fin angle variation. (b) The schematic cross-section view of channel fin with respect to different fin angles for devices with a fixed-top-fin width (W top), in this study.

Figure 2a shows the simulated bulk FinFET’s structure and the cross-section of fin channel. Table 1 lists the simulation settings and the achieved DC-characteristic parameters of each trapezoidal FinFET. The W top, bottom-fin width (W bottom), and the total fin width (W total), which is defined as 2 × W sidewall + W top, are also listed in Table 1. The value of W total is getting larger when the fin angle is getting smaller, and it is related to on-state current. The effective work function ranges from 4.4 to 4.5 eV, which is used to adjust the value of V th. The constant current method at 0.1 μA × W total/L g is used to extract the magnitude of V th, and the absolute value of the nominal V th of each different-fin-angle trapezoidal FinFET is 250 mV. For the comparison of RDF on trapezoidal bulk FinFETs, the simulation is based on the same V th, where the adopted device parameters are listed in Table 1. Figure 2b,c shows the large-scale statistical simulation method of RDF on the channel region. For RDF simulation, many discrete dopants dependent on the geometry are randomly generated in a large cube, where the dopant concentration in the large cuboid is equivalent to a channel doping concentration of 1.5 × 1018 cm−3. Then, the large cube is partitioned into many subcubes, where the distribution of RDs’ number follows Gaussian distribution, as shown in the right plot of Figure 2c. Then, a transformation of coordinate is performed on those subcubes to make them become trapezoidal-shaped channels and map them into 3D device channel regions. Notably, each coordinate of RDs is also transformed so that they appear in the trapezoidal-shaped channel exactly. To investigate the devices’ characteristics, a set of 3D drift-diffusion equations coupled with the density gradient equation for quantum correction is solved [13,14]. The mobility model used in the device simulation mainly follows our earlier work [15] which involves surface roughness, high-field saturation, and impurity scattering. Notably, the mobility model activated in our device simulation considers the influence of surface orientations on the on-state current by the term of effective electric field for every fin angle [16]. The mobility model is quantified with our recent device measurements for the best accuracy of simulation, and the characteristic fluctuation has been validated with the experimentally measured DC base band data from 15/20 CMOS devices [15]. For each statistical device simulation, 216 RD-fluctuated FinFET devices are randomly generated for every fin angle to estimate the magnitude of the RDF-induced characteristic fluctuation.

Figure 2
figure 2

The large-scale statistical device simulation method of RDF on the device’s channel region. (a) The schematic structure of the 16-nm-gate trapezoidal bulk FinFET device and the cross-section view of fin channel. (b) Discrete dopants are randomly distributed in a large cube with the average concentration of 1.5 × 1018 cm−3. The number of RDs is dependent on the magnitude of the fin angle. (c) The right plot is the bar chart of distribution of number of dopants of each fin-angle bulk FinFET. The left plot is the procedure of generating fluctuated cases. The cube is partitioned into many subcubes. The coordinate transform is performed on those subcubes to make them become trapezoidal-shaped channels and map them into device channel regions.

Table 1 The simulation settings of nominal bulk FinFET devices

Results and discussion

The inset of Figure 3 shows a TEM cross-section view of fabricated 16 nm n-type bulk FinFET device (gate length L g = 16 nm) with amorphous-based TiN/HfSiON gate stacks with an EOT of 1.0 nm. The channel fin width is 16 nm, and the fin height is 32 nm. To ensure the best accuracy of device simulation, the I D-V G curve of the FinFET at V D = 0.8 V is experimentally calibrated with measured data (symbols), as shown in Figure 3, where the extracted physical and process parameters are used for the following study.

Figure 3
figure 3

Plot of calibrated I D - V G curves. The red solid line is the I D-V G of simulation result, and the triangular symbols are experimental data. The inset shows the TEM cross-section view of the fabricated and measured device.

Figure 4 shows the on-/off-state current characteristics of the trapezoidal bulk FinFETs with the fixed W top. The plot of I off versus RDs’ number is shown in Figure 4a. The magnitude of I off of rectangle-shaped bulk FinFETs is small, and 70° bulk FinFET has large I off . In addition, the distribution of I off is getting more dispersive when the fin angle is getting smaller. Under the same W top, the phenomena are as a result of the weak lateral gate control of large bottom-fin width (i.e., small fin angle). The plot of I on versus RDs’ number is shown in Figure 4b. Though the W total of 70° bulk FinFET is large, the on-state should be the largest of all. However, in rectangle-shaped bulk FinFETs, the fin width is narrow enough to induce strong volume inversion, where the electron mobility is enhanced due to less surface roughness. Therefore, the on-state current is comparable in the rectangle-shape bulk FinFET with the 70° bulk FinFET. Figure 4c shows the plot of I off versus I on. The FinFET with large fin angle has better on-/off-state current ratio and wider distribution of on-/off-state current than that of the FinFET with relatively smaller fin angles.

Figure 4
figure 4

Plots of I off versus I on and values of σI off , σI on , averaged I off , and averaged I on . (a) The Ioff versus RDs’ number plot. (b) The I on versus RDs’ number plot. (c) The on/off current characteristic plot. (d) The value of σI off, σI on, averaged I off, and averaged I on of trapezoidal FinFET device with different fin angles.

Figure 5 shows the plot of the V th versus the number of RDs and the RDs’ number distribution for every fin angle. We note that each RD has the same size and concentration; therefore, the bulk FinFET with a small fin angle needs more amount of RDs’ number to achieve the same channel concentration due to large channel volume. As shown in Figure 5a, the trend of V th fluctuation is dominated by RDs’ number distributions, as shown in Figure 5b,c,d,e,f. The bulk FinFET whose fin angle is right angle has the smallest σV th. It has been known that the calculation of σV th follows the equation [17]:

Figure 5
figure 5

Plot of V th versus the number of RDs and the RDs’ number distribution. (a) The Vth versus the number of RDs. (b) to (f) RDs’ number distribution for every fin angle, where the μ is the mean and σ is the fluctuation.

$$ \sigma V\mathrm{t}\mathrm{h},\mathrm{R}\mathrm{D}\mathrm{F}=\frac{A_{\mathrm{VT}}}{\sqrt{W\times {L}_{\mathrm{g}}}}, $$

where A VT is the factor which is governed by manufacturing process and semiconductor material, W stands for the device’s width, and L g is the gate length. The denominator is dependent on the dimension and structure of devices. If we simply consider W as the effective channel width, which is defined by 2 × H f + W top for the rectangular-shape FinFET (or 2 × W sidewall + W top for various trapezoidal FinFETs), it cannot be used to explain our results of Figure 5a. It is because the estimation of Equation 1 is originally derived from planar MOSFETs, based on an assumption of the ability on inducing inversion charge is the same for whole gate region.

For FinFET devices, the ability of 3D vertical channel structure on inducing inversion charge is not the same due to the different coupling strengths of the top gate and the lateral gates. This phenomena could also be observed by examining the off-state (V G = 0 V) potential distribution, as shown in Figure 6a, where the high potential region is easy to induce charge and the low potential region in the lower fin would block off most transport electrons. As shown in plots of Figure 6b, if we slice the channel fin of bulk FinFET device (the left plot is for an ideal structure) along the lines in green, the conduction band energies of continuous-doping device and discrete-dopant device (we assume there is 1 RD on upper/lower fin in this case, respectively) at upper/lower fin are obtained, respectively. The same way is also applied on the 70° trapezoidal FinFET. The right two plots of Figure 6b indicate the off-state potential energies, and their fluctuated barriers are rather different not only for RDs appearing in different fin regions but also for devices with different fin angles.

Figure 6
figure 6

Off-state potential distribution of FinFET device and influence of one dopant on conduction band energy. (a) The off-state potential distribution of FinFET device with the right angle and 70° fin angle. (b) The influence of one dopant on upper-fin and lower-fin conduction band energy of FinFET device with the right angle and 70° fin angle. (c) The related value in (b), which can indicate the influence of dopant is dependent on the position and the fin angle and the ability of inducing inversion charge is not the same everywhere of gate.

Consequently, the influence of RDs on device’s subthreshold region is strongly dependent on the RDs’ position, the shape of channel, and the fin angle. Thus, the fin-angle-dependent ability on inducing inversion charge is indeed not the same for the entire gate region. Therefore, the argument of W top is not suitable to be regarded as the W in Equation 1. The effective W would be decreased with the fin angle getting smaller, and σV th will be increased. The dopant variation induced V th fluctuation is significant when the fin angle is small due to the less gate control. Therefore, based on the simulation results of Figures 4 and 5, in particular, from the analysis of RD’s position effect, we further propose an analytical expression to phenomenologically correct Equation 1:

$$ \sigma V\mathrm{t}\mathrm{h}=\frac{A_{\mathrm{VT}}^{\hbox{'}}\times {\left[\left(a\times {e}^{-b\times \theta}\right)\times {N}_{\mathrm{ch}}\right]}^{0.25}}{{}^{{\left({W}_{\mathrm{total}}\times {L}_g\right)}^{0.25}}}, $$

where the fitting coefficients a = 5.5 × 105 and b = 0.12. The \( {A}_{\mathrm{VT}}^{\hbox{'}} \) is a technologically dependent parameter except the channel dopant concentration and N ch is the channel doping concentration and θ is the fin angle which ranges from 70° to 90°. Notably, the denominator is dependent on the dimension and structure of devices and the factor 0.25 is mainly determined from the device structure which is different from the value of 0.5 used for planar MOSFET devices [18]. Two significant factors could be distinguished from this formula: one is the so-called structural effect as a result of the W total under the fixed gate length, and the other is related to the RDs’ position effect. The relationship between the effective channel dopants and the magnitude of the fin angle follows the trend of exponential decay. The influence of the fin angle dependent effective channel dopants dominates V th fluctuation as the result of the small variation on the magnitude of W total from variation of the fin angles. Not shown here, our model prediction is within 3% of accuracy, compared with the results in Figure 7a.

Figure 7
figure 7

RDF stimulation result and magnitudes of σV th , σ DIBL, and σ SS. (a) The RDF simulation result of bulk FinFET devices with respect to different fin angles. The magnitude of σV th is getting larger when the fin angle is getting smaller. (b) The magnitude of σDIBL versus the fin angle. The magnitude of σDIBL increases when the fin angle decreases owing to the wider bottom-fin width. (c) The magnitude of σSS versus the fin angle.

As shown in Figure 7, we estimate the fluctuations of the threshold voltage, the drain-induced barrier lowering (DIBL), and the subthreshold swing (SS) with respect to the fin angle. Consequently, as shown in Figure 7a, the V th fluctuation decreases when the fin angle increases for the trapezoidal bulk FinFET devices under the constant top-fin width. There is more than 7% increase on the V th fluctuation when the fin angle varies from 90° to 70° \( \left(\left(\frac{43.2-25.6}{250}\right)\times 100\%\approx 7\%\right) \), where the denominator is the nominal V th = 250 mV when θ = 90°. Figure 7b,c shows the plots of the fluctuations of DIBL (σDIBL) and SS (σSS) versus the fin angle, respectively. Both DIBL and SS fluctuations are getting significant when the fin angle is getting smaller. The relationship between DIBL as well as SS fluctuation and the fin angle corresponds with the V th analysis. The bulk FinFETs with a small fin angle suffers serious σDIBL (about 25.9% increases) due to large fin width. The increase of σSS is about 12.6% when the fin angle varies from 90° to 70°.


RDF on trapezoidal bulk FinFET devices with the fixed W top and different fin angles is studied by experimentally validated 3D device simulation. The bulk FinFET devices with large fin angle have small off-state current due to the strongest gate control. For the tested channel fin width of 8 nm, the on-state current of the 16-nm-gate HKMG bulk FinFET device is almost the same for all trapezoidal-shaped channels. Furthermore, V th’s fluctuation is affected by RDs’ number distribution under the same channel doping concentration and the right-angle bulk FinFET device has the smallest V th’s fluctuation among all devices with nonideal channel fins. We note that Equation 1 should be subject to further investigation for the calculation of σV th of bulk FinFET devices.

Definitely, an assumption that fixed the bottom-fin width and let the top-fin width be varied with the fin angle could be an interesting issue to be investigated in a future work. In addition, for bulk FinFET devices, a punch-through stopper is adopted for reducing the subthreshold leakage. The punch-through stopper may result in another RDF source owing to high substrate doping near the bottom channel. RDF simulation with including the impact of punch-through stopper could be subjected to further investigation, and it definitely will input more accurate estimation on the characteristic fluctuation.



fin-type field effect transistor


random dopant fluctuation


random dopant


short-channel effect

V th :

threshold voltage

W top :

top-fin width

W bottom :

bottom-fin width


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This work was supported in part by the Ministry of Science and Technology, Taiwan, under contracts No. NSC-102-2221-E-009-161 and No. MOST-103-2221-E-009-180 and by TSMC, Hsinchu, Taiwan, under a 2012–2013 grant. The authors would like to thank the instrumental supervision to deploy the sample measurement at Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan.

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Correspondence to Yiming Li.

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Authors’ contributions

W-TH performed the numerical simulation and data analysis, and YL conducted the whole study including data analysis and manuscript preparation. All the authors read and approved the final manuscript.

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Huang, WT., Li, Y. Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants. Nanoscale Res Lett 10, 116 (2015).

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  • Random dopant fluctuation
  • Characteristic fluctuation
  • Short-channel effect
  • Bulk FinFET
  • Channel fin angle
  • Trapezoidal
  • Ideal channel fin
  • Nonideal channel fin
  • Top-fin width