 Nano Express
 Open Access
 Published:
Electrical characteristic fluctuation of 16nmgate trapezoidal bulk FinFET devices with fixed topfin width induced by random discrete dopants
Nanoscale Research Letters volume 10, Article number: 116 (2015)
Abstract
In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16nmgate trapezoidal bulk fintype field effect transistor (FinFET) devices. The fixed topfin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed topfin width, we explore the impact of geometry and RDF on the on/offstate current and the threshold voltage (V _{th}) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the offstate current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the shortchannel effect and V _{th} variation degrade as the fin angle is getting smaller. The magnitude of the normalized σV _{th} increases 7% when the fin angle decreases from 90° to 70°.
Background
Scaling down the CMOS technology node beyond the sub20 nm causes the transistor to go through a transition from planar to multigate FETs such as bulk fintype field effect transistors (FinFETs) because of the requirement of better gate control and suppression on shortchannel effects (SCEs) [13]. In addition to the improvement on DC characteristics of individual device, however, continuously scaling not only overcomes challenges on fabrication but also suppresses systematic variation and random effects [4,5]. In practical fabrication, it is difficult to obtain uniform thickness along the height of the fin channel due to limitations in process technology [6]. The actual fins channel may be fabricated as trapezoidal shape and degrade the device performance by significant SCEs. For variability issues, there are many serious fluctuation sources such as random dopant fluctuation (RDF) [7], workfunction fluctuation [8], interface trap fluctuation [9], and the line edge roughness [10]. For lowstandbypower device technologies and applications, channel doping is still needed to adjust the threshold voltage (V _{th}) and RDF has been shown as the major source of variations for highΚ metal gate (HKMG) bulk FinFET devices [11] among various fluctuation factors. Recent researches on RDF and finshape effects were reported for FinFET devices; however, the studies on FinFET’s RDF were only considered for devices with a rectangularshape fin channel [12]. However, the channel fin is not always with an ideal shape owing to process challenges. To the best of our knowledge, a research which simultaneously considers the aforementioned issues has not been well investigated yet.
In this study, we explore the RDF on DC characteristics of 16nmgate trapezoidal bulk FinFETs with the fixed topfin width (W _{top}) condition. We further intensively analyze the on/offstate current characteristic and V _{th}’s fluctuation of the 16nmgate trapezoidal HKMG bulk FinFET. The article is organized as follows. The ‘Methods’ section introduces the simulation technique for studying the RDF on trapezoidal bulk FinFET devices with different fin angles and the same W _{top}. The ‘Results and discussion’ section focuses mainly on the analysis and discussion of characteristic fluctuation from RDF of 16nmgate trapezoidal HKMG bulk FinFET devices. Finally, we draw conclusions and suggest future work.
Methods
The device configuration and simulation technique
Figure 1a shows various TEM views of realistic shape of fabricated twochannel fin in 16nm technological node. Due to the process capabilities, the fin angles θ _{1} and θ _{2}, as shown in these two images, may vary with the lithography and etching, etc. Therefore, devices with different trapezoidal shapes are fabricated. In this study, we assume the topfin width is fixed at 8 nm for the 16nmgate HKMG bulk FinFET devices. Figure 1b shows the schematic crosssection view of channel fin for the identicalW _{top} setting. The fin angle (θ) is thus defined as the angle between the bottom line and sidewall and ranges from 70° to 90°. Besides the fixed W _{top}, the channel doping concentration, which means the needed number of impurity in the channel region increases when the fin angle is getting smaller, is set the same for all simulation cases.
Figure 2a shows the simulated bulk FinFET’s structure and the crosssection of fin channel. Table 1 lists the simulation settings and the achieved DCcharacteristic parameters of each trapezoidal FinFET. The W _{top}, bottomfin width (W _{bottom}), and the total fin width (W _{total}), which is defined as 2 × W _{sidewall} + W _{top}, are also listed in Table 1. The value of W _{total} is getting larger when the fin angle is getting smaller, and it is related to onstate current. The effective work function ranges from 4.4 to 4.5 eV, which is used to adjust the value of V _{th}. The constant current method at 0.1 μA × W _{total}/L _{g} is used to extract the magnitude of V _{th}, and the absolute value of the nominal V _{th} of each differentfinangle trapezoidal FinFET is 250 mV. For the comparison of RDF on trapezoidal bulk FinFETs, the simulation is based on the same V _{th}, where the adopted device parameters are listed in Table 1. Figure 2b,c shows the largescale statistical simulation method of RDF on the channel region. For RDF simulation, many discrete dopants dependent on the geometry are randomly generated in a large cube, where the dopant concentration in the large cuboid is equivalent to a channel doping concentration of 1.5 × 10^{18} cm^{−3}. Then, the large cube is partitioned into many subcubes, where the distribution of RDs’ number follows Gaussian distribution, as shown in the right plot of Figure 2c. Then, a transformation of coordinate is performed on those subcubes to make them become trapezoidalshaped channels and map them into 3D device channel regions. Notably, each coordinate of RDs is also transformed so that they appear in the trapezoidalshaped channel exactly. To investigate the devices’ characteristics, a set of 3D driftdiffusion equations coupled with the density gradient equation for quantum correction is solved [13,14]. The mobility model used in the device simulation mainly follows our earlier work [15] which involves surface roughness, highfield saturation, and impurity scattering. Notably, the mobility model activated in our device simulation considers the influence of surface orientations on the onstate current by the term of effective electric field for every fin angle [16]. The mobility model is quantified with our recent device measurements for the best accuracy of simulation, and the characteristic fluctuation has been validated with the experimentally measured DC base band data from 15/20 CMOS devices [15]. For each statistical device simulation, 216 RDfluctuated FinFET devices are randomly generated for every fin angle to estimate the magnitude of the RDFinduced characteristic fluctuation.
Results and discussion
The inset of Figure 3 shows a TEM crosssection view of fabricated 16 nm ntype bulk FinFET device (gate length L _{g} = 16 nm) with amorphousbased TiN/HfSiON gate stacks with an EOT of 1.0 nm. The channel fin width is 16 nm, and the fin height is 32 nm. To ensure the best accuracy of device simulation, the I _{D}V _{G} curve of the FinFET at V _{D} = 0.8 V is experimentally calibrated with measured data (symbols), as shown in Figure 3, where the extracted physical and process parameters are used for the following study.
Figure 4 shows the on/offstate current characteristics of the trapezoidal bulk FinFETs with the fixed W _{top}. The plot of I _{off} versus RDs’ number is shown in Figure 4a. The magnitude of I _{off} of rectangleshaped bulk FinFETs is small, and 70° bulk FinFET has large I _{off} . In addition, the distribution of I _{off} is getting more dispersive when the fin angle is getting smaller. Under the same W _{top}, the phenomena are as a result of the weak lateral gate control of large bottomfin width (i.e., small fin angle). The plot of I _{on} versus RDs’ number is shown in Figure 4b. Though the W _{total} of 70° bulk FinFET is large, the onstate should be the largest of all. However, in rectangleshaped bulk FinFETs, the fin width is narrow enough to induce strong volume inversion, where the electron mobility is enhanced due to less surface roughness. Therefore, the onstate current is comparable in the rectangleshape bulk FinFET with the 70° bulk FinFET. Figure 4c shows the plot of I _{off} versus I _{on}. The FinFET with large fin angle has better on/offstate current ratio and wider distribution of on/offstate current than that of the FinFET with relatively smaller fin angles.
Figure 5 shows the plot of the V _{th} versus the number of RDs and the RDs’ number distribution for every fin angle. We note that each RD has the same size and concentration; therefore, the bulk FinFET with a small fin angle needs more amount of RDs’ number to achieve the same channel concentration due to large channel volume. As shown in Figure 5a, the trend of V _{th} fluctuation is dominated by RDs’ number distributions, as shown in Figure 5b,c,d,e,f. The bulk FinFET whose fin angle is right angle has the smallest σV _{th}. It has been known that the calculation of σV _{th} follows the equation [17]:
where A _{VT} is the factor which is governed by manufacturing process and semiconductor material, W stands for the device’s width, and L _{g} is the gate length. The denominator is dependent on the dimension and structure of devices. If we simply consider W as the effective channel width, which is defined by 2 × H _{f} + W _{top} for the rectangularshape FinFET (or 2 × W _{sidewall} + W _{top} for various trapezoidal FinFETs), it cannot be used to explain our results of Figure 5a. It is because the estimation of Equation 1 is originally derived from planar MOSFETs, based on an assumption of the ability on inducing inversion charge is the same for whole gate region.
For FinFET devices, the ability of 3D vertical channel structure on inducing inversion charge is not the same due to the different coupling strengths of the top gate and the lateral gates. This phenomena could also be observed by examining the offstate (V _{G} = 0 V) potential distribution, as shown in Figure 6a, where the high potential region is easy to induce charge and the low potential region in the lower fin would block off most transport electrons. As shown in plots of Figure 6b, if we slice the channel fin of bulk FinFET device (the left plot is for an ideal structure) along the lines in green, the conduction band energies of continuousdoping device and discretedopant device (we assume there is 1 RD on upper/lower fin in this case, respectively) at upper/lower fin are obtained, respectively. The same way is also applied on the 70° trapezoidal FinFET. The right two plots of Figure 6b indicate the offstate potential energies, and their fluctuated barriers are rather different not only for RDs appearing in different fin regions but also for devices with different fin angles.
Consequently, the influence of RDs on device’s subthreshold region is strongly dependent on the RDs’ position, the shape of channel, and the fin angle. Thus, the finangledependent ability on inducing inversion charge is indeed not the same for the entire gate region. Therefore, the argument of W _{top} is not suitable to be regarded as the W in Equation 1. The effective W would be decreased with the fin angle getting smaller, and σV _{th} will be increased. The dopant variation induced V _{th} fluctuation is significant when the fin angle is small due to the less gate control. Therefore, based on the simulation results of Figures 4 and 5, in particular, from the analysis of RD’s position effect, we further propose an analytical expression to phenomenologically correct Equation 1:
where the fitting coefficients a = 5.5 × 10^{5} and b = 0.12. The \( {A}_{\mathrm{VT}}^{\hbox{'}} \) is a technologically dependent parameter except the channel dopant concentration and N _{ch} is the channel doping concentration and θ is the fin angle which ranges from 70° to 90°. Notably, the denominator is dependent on the dimension and structure of devices and the factor 0.25 is mainly determined from the device structure which is different from the value of 0.5 used for planar MOSFET devices [18]. Two significant factors could be distinguished from this formula: one is the socalled structural effect as a result of the W _{total} under the fixed gate length, and the other is related to the RDs’ position effect. The relationship between the effective channel dopants and the magnitude of the fin angle follows the trend of exponential decay. The influence of the fin angle dependent effective channel dopants dominates V _{th} fluctuation as the result of the small variation on the magnitude of W _{total} from variation of the fin angles. Not shown here, our model prediction is within 3% of accuracy, compared with the results in Figure 7a.
As shown in Figure 7, we estimate the fluctuations of the threshold voltage, the draininduced barrier lowering (DIBL), and the subthreshold swing (SS) with respect to the fin angle. Consequently, as shown in Figure 7a, the V _{th} fluctuation decreases when the fin angle increases for the trapezoidal bulk FinFET devices under the constant topfin width. There is more than 7% increase on the V _{th} fluctuation when the fin angle varies from 90° to 70° \( \left(\left(\frac{43.225.6}{250}\right)\times 100\%\approx 7\%\right) \), where the denominator is the nominal V _{th} = 250 mV when θ = 90°. Figure 7b,c shows the plots of the fluctuations of DIBL (σDIBL) and SS (σSS) versus the fin angle, respectively. Both DIBL and SS fluctuations are getting significant when the fin angle is getting smaller. The relationship between DIBL as well as SS fluctuation and the fin angle corresponds with the V _{th} analysis. The bulk FinFETs with a small fin angle suffers serious σDIBL (about 25.9% increases) due to large fin width. The increase of σSS is about 12.6% when the fin angle varies from 90° to 70°.
Conclusions
RDF on trapezoidal bulk FinFET devices with the fixed W _{top} and different fin angles is studied by experimentally validated 3D device simulation. The bulk FinFET devices with large fin angle have small offstate current due to the strongest gate control. For the tested channel fin width of 8 nm, the onstate current of the 16nmgate HKMG bulk FinFET device is almost the same for all trapezoidalshaped channels. Furthermore, V _{th}’s fluctuation is affected by RDs’ number distribution under the same channel doping concentration and the rightangle bulk FinFET device has the smallest V _{th}’s fluctuation among all devices with nonideal channel fins. We note that Equation 1 should be subject to further investigation for the calculation of σV _{th} of bulk FinFET devices.
Definitely, an assumption that fixed the bottomfin width and let the topfin width be varied with the fin angle could be an interesting issue to be investigated in a future work. In addition, for bulk FinFET devices, a punchthrough stopper is adopted for reducing the subthreshold leakage. The punchthrough stopper may result in another RDF source owing to high substrate doping near the bottom channel. RDF simulation with including the impact of punchthrough stopper could be subjected to further investigation, and it definitely will input more accurate estimation on the characteristic fluctuation.
Abbreviations
 FinFET:

fintype field effect transistor
 RDF:

random dopant fluctuation
 RD:

random dopant
 SCE:

shortchannel effect
 V _{th} :

threshold voltage
 W _{top} :

topfin width
 W _{bottom} :

bottomfin width
References
 1.
Mil’shtein S, Devarakonda L, Zanchi B, Palma J. 3D modeling of dualgate FinFET. Nanoscale Res Lett. 2012;7:625.
 2.
Magnone P, Subramanian V, Parvais B, Mercha A, Pace C, Dehan M, et al. Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices. Microelectron Eng. 2008;85:1728–31.
 3.
Kuhn KJ, Avci U, Cappellani A, Giles MD, Haverty M, Kim S, et al. The ultimate CMOS device and beyond. In: Proceedings of the IEEE International Electron Devices Meeting: December 10–13, vol. 2012. San Francisco, CA: IEEE; 2012. p. 171–4.
 4.
Li Y, Hwang CH, Han MH. Simulation of characteristic variation in 16nmgate FinFET devices due to intrinsic parameter fluctuations. Nanotechnology. 2010;21:095203.
 5.
Matsukawa T, O’uchi S, Endo K, Ishikawa Y, Yamauchi H, Liu YX, et al. Comprehensive analysis of variability sources of FinFET characteristics. In: Proceedings of the IEEE Symposium on VLSI Technology: June 16–18, vol. 2009. Honolulu, HI: IEEE; 2009. p. 118–9.
 6.
Li Y, Hwang CH. Effect of fin angle on electrical characteristics of nanoscale roundtopgate bulk FinFETs. IEEE Trans Electron Devices. 2007;54:3426–9.
 7.
Li Y, Hwang CH. Discretedopantinduced characteristic fluctuations in 16 nm multiplegate silicononinsulator devices. J Appl Phys. 2007;102:084509.
 8.
Nam H, Shin C. Study of highκ/metalgate work function variation in FinFET: the modified RGG concept. IEEE Electron Device Lett. 2013;34:1560–2.
 9.
Wang X, Cheng B, Brown A, Millar C, Kuang JB, Nassif S, et al. Impact of statistical variability and charge trapping on 14 nm SOI finFET SRAM cell stability. In: Proceedings of the IEEE European SolidState Device Research Conference: September 16–20, vol. 2013. Bucharest, Romania: IEEE; 2013. p. 234–7.
 10.
Chen CH, Li Y, Chen CY, Chen YY, Hsu SC, Huang WT, et al. Mobility model extraction for surface roughness of SiGe along (110) and (100) orientations in HKMG bulk FinFET devices. Microelectron Eng. 2011;109:357–9.
 11.
Bohr M. The evolution of scaling from the homogeneous era to the heterogeneous era. In: Proceedings of the IEEE International Electron Devices Meeting: December 5–7. Washington, DC: IEEE; 2011. p. 1–6.
 12.
Leung G, Chui CO. Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs. IEEE Electron Device Lett. 2012;33:767–9.
 13.
Li Y, Liu JL, Chao TS, Sze SM. A new parallel adaptive finite volume method for the numerical simulation of semiconductor devices. Comput Phys Commun. 2001;142:285–9.
 14.
Ancona MG. Densitygradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices. J Comp Elect. 2011;10:65–97.
 15.
Li Y, Yu SM, Hwang JR, Yang FL. Discrete dopant fluctuated 20 nm/15 nmgate planar CMOS. IEEE Trans Electron Devices. 2008;55:1449–55.
 16.
Takagi SI, Toriumi A, Iwase M, Tango H. On the universality of inversion layer mobility in Si MOSFET’s: part II—effects of surface orientation. IEEE Trans Electron Devices. 1994;41:2363–8.
 17.
Takeuchi K, Nishida A, Hiramoto T. Random fluctuations in scaled MOS devices. In: Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices: September 9–11, vol. 2009. San Diego, CA: IEEE; 2009. p. 1–7.
 18.
Li Y, Hwang CH. Discretedopantfluctuated threshold voltage rolloff in sub16 nm bulk fintype field effect transistors. Jpn J Appl Phys. 2008;47:2580–4.
Acknowledgements
This work was supported in part by the Ministry of Science and Technology, Taiwan, under contracts No. NSC1022221E009161 and No. MOST1032221E009180 and by TSMC, Hsinchu, Taiwan, under a 2012–2013 grant. The authors would like to thank the instrumental supervision to deploy the sample measurement at Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan.
Author information
Additional information
Competing interests
The authors declare that they have no competing interests.
Authors’ contributions
WTH performed the numerical simulation and data analysis, and YL conducted the whole study including data analysis and manuscript preparation. All the authors read and approved the final manuscript.
Rights and permissions
Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (https://creativecommons.org/licenses/by/4.0), which permits use, duplication, adaptation, distribution, and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
About this article
Cite this article
Huang, W., Li, Y. Electrical characteristic fluctuation of 16nmgate trapezoidal bulk FinFET devices with fixed topfin width induced by random discrete dopants. Nanoscale Res Lett 10, 116 (2015) doi:10.1186/s1167101507390
Received
Accepted
Published
DOI
Keywords
 Random dopant fluctuation
 Characteristic fluctuation
 Shortchannel effect
 Bulk FinFET
 Channel fin angle
 Trapezoidal
 Ideal channel fin
 Nonideal channel fin
 Topfin width