Fig. 4
a Hysteresis loop characteristics with voltage shift as large as 1.25 V are observed for both n- and p-MOS capacitors when the gate bias is swept from inversion to accumulation conditions. b I d -V g and c memory endurance characteristics of Ge QD floating gate memories under a +8 V/60 msec pulse programing and a −5 V/30 msec pulse erasing. The I d -V g characteristics are swept from 0 to 2 V. ΔV th of ~0.42 V is achieved with negligible ΔV th degradation following 105 program/erase cycles