Open Access

Capacitance-Voltage Characteristics of Thin-film Transistors Fabricated with Solution-Processed Semiconducting Carbon Nanotube Networks

Nanoscale Research Letters201510:291

Received: 20 May 2015

Accepted: 2 July 2015

Published: 15 July 2015


We report the capacitance-voltage (C-V) measurements on thin-film transistors (TFTs) using solution-processed semiconducting carbon nanotube networks with different densities and channel lengths. From the measured C-V characteristics, gate capacitance and field-effect mobility (up to ~50 cm2 V−1 s−1) of the TFTs were evaluated with better precision compared with the results obtained from calculated gate capacitance. The C-V characteristics measured under different frequencies further enabled the extraction and analysis of the interface trap density at the nanotube-dielectric layer interface, which was found to increase significantly as the network density increases. The results presented here indicate that C-V measurement is a powerful tool to assess the electrical performance and to investigate the carrier transport mechanism of TFTs based on carbon nanotubes.


Carbon nanotube network Thin-film transistor Gate capacitance Interface trap density


Owing to its extremely large carrier mean free path and high mobility, semiconducting single-wall carbon nanotube (sSWCNT) is considered as one of the promising candidates for beyond-silicon electronics [13]. However, despite the tremendous progress made in individual sSWCNT electronic device and circuit research, scalable fabrication and integration of large quantities of devices with uniform performance remain to be greatly challenging, largely due to the structure heterogeneity of carbon nanotubes and difficulties in assembling them with nanoscale precision [4]. On the other hand, using random networks of carbon nanotubes for applications in thin-film transistors (TFTs) has recently shown great promise. Such devices offer mechanical flexibility and optical transparency and can be easily fabricated in a scalable fashion with far superior device performance and long-term air-stability compared with amorphous silicon or organic semiconductors [511]. Among various approaches used for assembling random carbon nanotube networks, solution-processed semiconductor-enriched carbon nanotubes possess additional advantages of low-cost and room temperature processes [6, 810, 12]. With the ongoing pavement towards reliable dispersion of longer nanotubes with higher purity separation process [13], large-scale, high-performance, flexible carbon nanotube TFTs have already found wide applications in compliant integrated circuits, organic light-emitting displays, and electronic skins [5, 9, 11, 14].

One important device parameter used for assessing the electrical performance of TFT is its field-effect mobility. Precise evaluation of the field-effect mobility is crucial for the fair comparison of device performance between different material platforms. In order to extract the mobility, information about the gate capacitance is needed, which reflects the electrostatic coupling between the channel semiconductor and the planar gate electrode. For carbon nanotube transistors, the gate capacitances are typically calculated from either an ideal parallel-plate model or a more rigorous cylindrical model by considering the electrostatic coupling between nanotubes [5, 7, 15, 16]. The former apparently overestimates the gate capacitance due to low coverage of nanotubes in the channel and thereby underestimates the device mobility, while the latter sometimes overestimates the mobility due to uncertainty in determining tube diameter and density for a random network. In principle, the gate capacitance can be experimentally determined from the capacitance-voltage (C-V) characteristics of the transistors, which should provide a more precise evaluation of the device performance. Additionally, C-V measurement is a powerful tool to get deep physical insights of the electronic performance of metal-insulator-semiconductor (MIS) structures [17, 18].

Here, in this paper, we report the C-V measurements on solution-processed carbon nanotube TFTs with various network densities. Based on the C-V characteristics, field-effect mobility of the devices was accurately assessed and compared with values estimated using both parallel-plate and cylindrical capacitance models. In addition, the C-V characteristics were measured at different frequencies to allow further extraction of the interface trap density, which could shed light on the quality and cleanness of the interface between the solution-processed carbon nanotubes and the gate dielectric layer.


High-purity semiconducting SWCNTs with a purity of approximated 99 % (purchased from NanoIntegris, Inc.) were used as the channel semiconductor. The device structure of the TFTs used in this study is presented in Fig. 1a, which incorporates a local back-gate. Both overlap gate and underlap gate devices were fabricated on the same substrate. The detailed fabrication process resembles the one reported in our previous publications [4, 8]. Briefly, electron beam (e-beam) evaporated Ti/Au (5/50 nm) was patterned as the gate (G) electrode using photolithography, followed by deposition of 25 nm of Al2O3 and 10 nm of SiO2 as the gate dielectric layer using atomic layer deposition and e-beam evaporation, respectively. Uniform networks of sSWCNTs were obtained by functionalizing the substrate surface with amine-group (immersing in 0.1 g ml−1 poly-l-lysine solution for 5 min) before immersing into 0.01 mg ml−1 sSWCNT solutions. The density of the carbon nanotube network can be effectively controlled by adjusting the deposition time as shown in Fig. 1b–e. The atomic force microscopy (AFM) images indicate a monotonic increase in network density as the deposition time increases from 5 to 90 min. On top of the carbon nanotube network, source/drain (S/D) electrodes, composed of 0.5 nm Ti and 50 nm Pd, were patterned and the carbon nanotubes outside the channel region were subsequently etched away using O2 plasma. Finally, via holes were patterned and opened by HF etching to expose the gate probing pads.
Fig. 1

Thin-film transistors based on solution-processed random networks of semiconducting carbon nanotubes. a Schematic of the device structure. be AFM images of the networks deposited by immersing the substrate into 0.01 mg ml−1 sSWCNT solution for 5, 15, 30, and 90 min, respectively. Scale bars in be, 1 μm

Both current-voltage (I-V) and C-V characteristics were measured using an Agilent B1500A Semiconductor Device Parameter Analyzer. For I-V measurements, devices with overlap gate configuration (G completely overlaps with S/D) were used in order to eliminate the un-gated region and minimize the access resistance. For C-V measurements, underlap gate structure was adopted (gate length L g of 3, 8, and 16 μm for channel length L of 4, 10, and 20 μm, respectively) to minimize the parasitic capacitance.

Results and Discussion

I-V Characteristics

I-V characterization was performed on the above-described solution-processed carbon nanotube TFTs with various channel lengths and network densities (as the nanotube deposition time increases from 5 up to 90 min). Figure 2a shows the representative transfer characteristics (I SD-V GS) of devices with different nanotube network densities measured at V DS = −5 V. All devices presented in Fig. 2a have the same channel length (L) and width (W) of 10 and 100 μm, respectively. All I SD-V GS curves show p-type behavior with gradually decreasing on/off current ratio (I on/I off) and increasing on-current (I on) as the nanotube density increases. More systematic measurements were carried out on devices with different channel lengths and the results are summarized in Fig. 2b–d. Device performance metrics of the TFTs, including I on/I off, unit width normalized on-current (I on/W) and transconductance (g m/W), are extracted from the measured I SD-V GS curves (shown in Additional file 1: Figure S1 of the Electronic Supplementary Material) to allow the analysis of their dependence on channel length and network density.
Fig. 2

I SD-V GS characteristics of the TFTs with overlap gates. a I SD-V GS curves measured at a VDS of −5 V for devices (L = 10 μm, W = 100 μm) with different deposition times and thereby different network densities. bd On/off ratio vs. L (b), width normalized on-current vs. 1/L (c), and width normalized transconductance vs. 1/L (d) for devices with different network densities

For all the device metrics listed above, the most significant change occurs as the deposition time increases from 5 to 15 min, in accordance to the evolution of network density. According to Fig. 2b, devices with lower network density and larger channel length tend to have higher on/off ratio (up to 104), which is resulted from the lower probability for metallic nanotubes to form percolating pathways between the S/D in looser network and long-channel devices. On the other hand, lower network density also leads to significant decrease in I on and g m as shown in Fig. 2c, d. This trade-off is an important design consideration for optimizing device performance of carbon nanotube TFTs targeting different applications. According to our previous studies, low network density long-channel devices, with high I on/I off, can be used for compliant digital electronics or as switches in backplane, while high-density short-channel ones are ideal for high-frequency applications [8, 9, 14]. Additionally, both I on/W and g m/W are approximately proportional to the reciprocal of channel length (1/L), which is in agreement with conventional field-effect transistor operation theory and also indicates the excellent uniformity of nanotube networks in our TFTs. The TFTs with shortest channels exhibit on-current and transconductance as high as ~30 μA μm−1 and ~4.5 μS μm−1, respectively, which is respectable performance for a solution-processed approach.

C-V Characteristics

In order to minimize the effect of parasitic capacitance on C-V measurements, devices with underlap gate electrode were used whose optical microscope images are shown in Fig. 3a. Such devices have channel lengths L (i.e., the separation between S/D electrodes) of 4, 10, and 20 μm, while the underlapped gate fingers have lengths L g of 3, 8, and 16 μm, respectively. L g instead of L was used when calculating the area for unit-area gate capacitance.
Fig. 3

C-V characteristics measured from nanotube TFTs with underlap gates. a Optical micrographs of underlap gate devices with different gate length of 3 μm (top), 8 μm (middle), and 16 μm (bottom). b C-V characteristics for devices (L = 20 μm, W = 200 μm) with different network densities measured at a frequency of 100 kHz. c Unit-area gate capacitance extracted from the measured C-V characteristics (red circle), calculated from parallel-plate model (black dashed line), and calculated from cylindrical model (blue dash line) plotted as a function of nanotube network density. d Device mobility extracted using the experimentally measured gate capacitance, plotted as a function of channel length and for different deposition times

C-V characteristics of devices with different channel lengths and nanotube network densities were measured over a frequency range of 2 kHz~1 MHz and the results are shown in Additional file 1: Figures S2 and S3. Figure 3b shows the representative C-V curves of TFTs (L g = 16 μm, W = 200 μm) with different network densities measured at a frequency of 100 kHz. The measured C-V curves in Fig. 3b generally resemble the trend observed in the I-V curves (Fig. 2), which is understandable considering the fact that gate modulation decreases with increasing deposition time and nanotube density as a result of more metallic pathways.

Additional file 1: Figure S4b shows the on-state capacitance (V GS = −5 V) plotted as a function of channel area (L g × W), where the unit-area gate capacitance can be deduced from the slope of linear fit of the data points. The experimentally determined gate capacitance from Additional file 1: Figure S4b was summarized and plotted as a function of nanotube density in Fig. 3c. Also presented are the parallel-plate capacitance (black dashed line), which was also experimentally measured using on-chip capacitors fabricated with the same dielectric layer as the TFTs (see Additional file 1: Figure S4a), and that calculated from the cylindrical model (blue dashed lines) using the equation reported in the literature [15] with an estimated average nanotube diameter of 1.4 nm. From the results, it is obvious that the parallel-plate model overestimates the gate capacitance while the cylindrical model underestimates it. This manifests the necessity of using C-V characteristics to accurately evaluate the gate capacitance and mobility.

Analysis of C-V Characteristics

Based on the measured gate capacitance, the field-effect mobility of the devices can be extracted using the following equation:
$$ \mu =\frac{L}{V_d{C}_{\mathrm{ox}}W}\frac{d{I}_g}{d{V}_g}=\frac{L}{V_d{C}_{\mathrm{ox}}}\frac{g_m}{W}. $$

Figure 3d shows the mobility as a function of channel length for devices with different deposition times. For all measured devices, the mobility increases initially with channel length and then saturates at a channel length of around 50 μm. For short-channel devices, the current is mostly limited by nanotube-electrode contact resistance instead of channel resistance. As a result, increase in channel length would lead to increase in the extracted field-effect mobility, until L ~ 50 μm when the channel resistance begins to take the dominance over contact resistance. The highest mobility of our devices is ~50 cm2 V−1 s−1, orders of magnitude higher than that of amorphous silicon and most organic semiconductors, making sSWCNTs ideal candidate for high-performance, solution-processed flexible TFTs.

Further analysis of the C-V data can lead to deeper physical insights of the device performance, such as the interface trap density (D it) at the nanotube and gate dielectric interface. The interface trap density can be extracted from C-V characteristics measured at high and low frequencies using the equation below [8, 17]:
$$ {D}_{\mathrm{it}}=\frac{C_{\mathrm{LF}}-{C}_{\mathrm{HF}}}{q\left(1-\frac{C_{\mathrm{LF}}}{C_{\mathrm{ox}}}\right)\left(1-\frac{C_{\mathrm{HF}}}{C_{\mathrm{ox}}}\right)LW} $$
where C LF and C HF are the low- and high-frequency capacitance, respectively, and q = 1.6 × 10−19 C. Figure 4a, b shows the extracted D it plotted as a function of deposition time and nanotube network density, respectively. The results indicate that the interface trap density could increase drastically as the deposition time/network density increases. Because the nanotube networks in our devices are assembled using a solution-based process, longer deposition time may lead to more residues from the solvent such as excessive surfactant or dust particles, which could degrade the cleanness of surface of the resulting carbon nanotube network, leading to significantly more interface traps. Because D it has negative impact on the overall device performance (e.g., lead to a worse subthreshold slope), it is important to keep it as low as possible. It should be pointed out that the real D it is underestimated using the strategy here due to the low coverage of sSWCNTs in the channel region. Nevertheless, our results show that C-V characterization can be a powerful tool to unveil more insights of the carbon nanotube TFT performance.
Fig. 4

Interface trap density of solution-processed carbon nanotube TFTs. a, b Relationship between extracted interface trap density and deposition time (a) and nanotube network density (b)


In summary, we have fabricated high-performance TFTs using solution-processed sSWCNT network as the channel material. Systematic I-V and C-V characterizations were performed to study the relationship between various device performance metrics and nanotube density. We have also shown that the C-V measurements could lead to more accurate assessment of gate capacitance which in turn results in the evaluation of device mobility with a higher accuracy than other most widely adopted models. Finally, interface trap densities were also extracted from the C-V measurements and the results indicate that longer nanotube deposition time would lead to significantly more interface traps. The results presented here indicate that C-V measurement is a powerful means for the accurate evaluation of the performance of nanotube TFTs and the investigation of their carrier transport mechanism, both of which are important for further device optimization.



This work was partially funded by Michigan State University and the National Science Foundation under Grant ECCS-1549888.

Authors’ Affiliations

Department of Electrical and Computing Engineering, Michigan State University


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